From: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
commit df9cf852ca3099feb8fed781bdd5d3863af001c8 upstream.
Widebus allows the DP controller to operate in 2 pixel per clock mode.
The mode validation logic validates the mode->clock against the max
DP pixel clock. However the max DP pixel clock limit assumes widebus
is already enabled. Adjust the mode validation logic to only compare
the adjusted pixel clock which accounts for widebus against the max DP
pixel clock. Also fix the mode validation logic for YUV420 modes as in
that case as well, only half the pixel clock is needed.
Cc: stable@xxxxxxxxxxxxxxx
Fixes: 757a2f36ab09 ("drm/msm/dp: enable widebus feature for display port")
Fixes: 6db6e5606576 ("drm/msm/dp: change clock related programming for YUV420 over DP")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Tested-by: Dale Whinham <daleyo@xxxxxxxxx>
Patchwork: https://patchwork.freedesktop.org/patch/635789/
Link: https://lore.kernel.org/r/20250206-dp-widebus-fix-v2-1-cb89a0313286@xxxxxxxxxxx
Signed-off-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/dp/dp_display.c | 11 ++++++-----
drivers/gpu/drm/msm/dp/dp_drm.c | 5 ++++-
2 files changed, 10 insertions(+), 6 deletions(-)
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -937,16 +937,17 @@ enum drm_mode_status msm_dp_bridge_mode_
return -EINVAL;
}
- if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
- return MODE_CLOCK_HIGH;
-
msm_dp_display = container_of(dp, struct msm_dp_display_private, msm_dp_display);
link_info = &msm_dp_display->panel->link_info;
- if (drm_mode_is_420_only(&dp->connector->display_info, mode) &&
- msm_dp_display->panel->vsc_sdp_supported)
+ if ((drm_mode_is_420_only(&dp->connector->display_info, mode) &&
+ msm_dp_display->panel->vsc_sdp_supported) ||
+ msm_dp_wide_bus_available(dp))
mode_pclk_khz /= 2;
+ if (mode_pclk_khz > DP_MAX_PIXEL_CLK_KHZ)
+ return MODE_CLOCK_HIGH;
+
mode_bpp = dp->connector->display_info.bpc * num_components;
if (!mode_bpp)
mode_bpp = default_bpp;
--- a/drivers/gpu/drm/msm/dp/dp_drm.c
+++ b/drivers/gpu/drm/msm/dp/dp_drm.c
@@ -257,7 +257,10 @@ static enum drm_mode_status msm_edp_brid
return -EINVAL;
}
- if (mode->clock > DP_MAX_PIXEL_CLK_KHZ)
+ if (msm_dp_wide_bus_available(dp))
+ mode_pclk_khz /= 2;
+
+ if (mode_pclk_khz > DP_MAX_PIXEL_CLK_KHZ)
return MODE_CLOCK_HIGH;
/*
Patches currently in stable-queue which might be from quic_abhinavk@xxxxxxxxxxx are
queue-6.13/drm-msm-dsi-phy-protect-phy_cmn_clk_cfg0-updated-fro.patch
queue-6.13/drm-msm-dsi-phy-do-not-overwite-phy_cmn_clk_cfg1-whe.patch
queue-6.13/drm-msm-dpu-disable-dither-in-phys-encoder-cleanup.patch
queue-6.13/drm-msm-dpu-skip-watchdog-timer-programming-through-.patch
queue-6.13/drm-msm-dpu-don-t-leak-bits_per_component-into-rando.patch
queue-6.13/drm-msm-dp-account-for-widebus-and-yuv420-during-mode-validation.patch
queue-6.13/drm-msm-dsi-phy-protect-phy_cmn_clk_cfg1-against-clo.patch
queue-6.13/drm-msm-dpu-enable-dpu_wb_input_ctrl-for-dpu-5.x.patch
