This is a note to let you know that I've just added the patch titled
phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation
to the 6.13-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
phy-freescale-fsl-samsung-hdmi-clean-up-fld_tg_code-.patch
and it can be found in the queue-6.13 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit 9642b24932cbeada57c19fe2675b44661f90c2eb
Author: Adam Ford <aford173@xxxxxxxxx>
Date: Sat Oct 26 08:19:59 2024 -0500
phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation
[ Upstream commit d567679f2b6a8bcea20589bbea6488c0236886cd ]
Currently, the calcuation for fld_tg_code is based on a lookup table,
but there are gaps in the lookup table, and frequencies in these
gaps may not properly use the correct divider. Based on the description
of FLD_CK_DIV, the internal PLL frequency should be less than 50 MHz,
so directly calcuate the value of FLD_CK_DIV from pixclk.
This allow for proper calcuation of any pixel clock and eliminates a
few gaps in the LUT.
Since the value of the int_pllclk is in Hz, do the fixed-point
math in Hz to achieve a more accurate value and reduces the complexity
of the caluation to 24MHz * (256 / int_pllclk).
Fixes: 6ad082bee902 ("phy: freescale: add Samsung HDMI PHY")
Signed-off-by: Adam Ford <aford173@xxxxxxxxx>
Reviewed-by: Frieder Schrempf <frieder.schrempf@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20241026132014.73050-3-aford173@xxxxxxxxx
Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
index d3ccf547ba1c2..17c3786c2f667 100644
--- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
+++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c
@@ -331,25 +331,17 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
{
u32 pclk = cfg->pixclk;
u32 fld_tg_code;
- u32 pclk_khz;
- u8 div = 1;
-
- switch (cfg->pixclk) {
- case 22250000 ... 47500000:
- div = 1;
- break;
- case 50349650 ... 99000000:
- div = 2;
- break;
- case 100699300 ... 198000000:
- div = 4;
- break;
- case 205000000 ... 297000000:
- div = 8;
- break;
+ u32 int_pllclk;
+ u8 div;
+
+ /* Find int_pllclk speed */
+ for (div = 0; div < 4; div++) {
+ int_pllclk = pclk / (1 << div);
+ if (int_pllclk < (50 * MHZ))
+ break;
}
- writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12));
+ writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12));
/*
* Calculation for the frequency lock detector target code (fld_tg_code)
@@ -362,10 +354,8 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
* settings rounding up always too. TODO: Check if that is
* correct.
*/
- pclk /= div;
- pclk_khz = pclk / 1000;
- fld_tg_code = 256 * 1000 * 1000 / pclk_khz * 24;
- fld_tg_code = DIV_ROUND_UP(fld_tg_code, 1000);
+
+ fld_tg_code = DIV_ROUND_UP(24 * MHZ * 256, int_pllclk);
/* FLD_TOL and FLD_RP_CODE taken from downstream driver */
writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code),
