From: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
commit b8c3a2502a205321fe66c356f4b70cabd8e1a5fc upstream.
The only difference between 5 and 6 is the new counters snapshotting
group, without the following counters snapshotting enabling patches,
it's impossible to utilize the feature in a PEBS record. It's safe to
share the same code path with format 5.
Add format 6, so the end user can at least utilize the legacy PEBS
features.
Fixes: a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support")
Signed-off-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Link: https://lore.kernel.org/r/20241216204505.748363-1-kan.liang@xxxxxxxxxxxxxxx
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/x86/events/intel/ds.c | 1 +
1 file changed, 1 insertion(+)
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2496,6 +2496,7 @@ void __init intel_ds_init(void)
x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
break;
+ case 6:
case 5:
x86_pmu.pebs_ept = 1;
fallthrough;
Patches currently in stable-queue which might be from kan.liang@xxxxxxxxxxxxxxx are
queue-6.12/perf-x86-intel-ds-add-pebs-format-6.patch
queue-6.12/perf-x86-intel-fix-bitmask-of-ocr-and-frontend-events-for-lnc.patch
queue-6.12/perf-x86-intel-uncore-add-clearwater-forest-support.patch
queue-6.12/fork-avoid-inappropriate-uprobe-access-to-invalid-mm.patch
