Patch "drm/amd/display: Add a left edge pixel if in YCbCr422 or YCbCr420 and odm" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amd/display: Add a left edge pixel if in YCbCr422 or YCbCr420 and odm

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-add-a-left-edge-pixel-if-in-ycbcr422.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 14a54868aaad5c6c93d24c5f5d5d0a5836064a05
Author: Peterson Guo <peterson.guo@xxxxxxx>
Date:   Thu Nov 7 19:20:02 2024 -0500

    drm/amd/display: Add a left edge pixel if in YCbCr422 or YCbCr420 and odm
    
    [ Upstream commit 63e7ee677c74e981257cedfdd8543510d09096ba ]
    
    [WHY]
    On some cards when odm is used, the monitor will have 2 separate pipes
    split vertically. When compression is used on the YCbCr colour space on
    the second pipe to have correct colours, we need to read a pixel from the
    end of first pipe to accurately display colours. Hardware was programmed
    properly to account for this extra pixel but it was not calculated
    properly in software causing a split screen on some monitors.
    
    [HOW]
    The fix adjusts the second pipe's viewport and timings if the pixel
    encoding is YCbCr422 or YCbCr420.
    
    Cc: Mario Limonciello <mario.limonciello@xxxxxxx>
    Cc: Alex Deucher <alexander.deucher@xxxxxxx>
    Cc: stable@xxxxxxxxxxxxxxx
    Reviewed-by: George Shen <george.shen@xxxxxxx>
    Signed-off-by: Peterson Guo <peterson.guo@xxxxxxx>
    Signed-off-by: Alex Hung <alex.hung@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 04b370e7e732..6688c40f3c70 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1899,6 +1899,7 @@ bool dcn20_split_stream_for_odm(
 
 	if (prev_odm_pipe->plane_state) {
 		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
+		struct output_pixel_processor *opp = next_odm_pipe->stream_res.opp;
 		int new_width;
 
 		/* HACTIVE halved for odm combine */
@@ -1932,7 +1933,28 @@ bool dcn20_split_stream_for_odm(
 		sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
 				sd->ratios.horz_c, sd->h_active - sd->recout.x));
 		sd->recout.x = 0;
+
+		/*
+		 * When odm is used in YcbCr422 or 420 colour space, a split screen
+		 * will be seen with the previous calculations since the extra left
+		 *  edge pixel is accounted for in fmt but not in viewport.
+		 *
+		 * Below are calculations which fix the split by fixing the calculations
+		 * if there is an extra left edge pixel.
+		 */
+		if (opp && opp->funcs->opp_get_left_edge_extra_pixel_count
+				&& opp->funcs->opp_get_left_edge_extra_pixel_count(
+					opp, next_odm_pipe->stream->timing.pixel_encoding,
+					resource_is_pipe_type(next_odm_pipe, OTG_MASTER)) == 1) {
+			sd->h_active += 1;
+			sd->recout.width += 1;
+			sd->viewport.x -= dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1));
+			sd->viewport_c.x -= dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1));
+			sd->viewport_c.width += dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1));
+			sd->viewport.width += dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1));
+		}
 	}
+
 	if (!next_odm_pipe->top_pipe)
 		next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
 	else
@@ -2905,6 +2927,7 @@ bool dcn20_fast_validate_bw(
 			ASSERT(0);
 		}
 	}
+
 	/* Actual dsc count per stream dsc validation*/
 	if (!dcn20_validate_dsc(dc, context)) {
 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =




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