From: Catalin Marinas <catalin.marinas@xxxxxxx> commit 78615c4ddb73bd4a7f13ec4bab60b974b8fc6faa upstream. Patch series "Move the ARCH_DMA_MINALIGN definition to asm/cache.h". The ARCH_KMALLOC_MINALIGN reduction series defines a generic ARCH_DMA_MINALIGN in linux/cache.h: https://lore.kernel.org/r/20230612153201.554742-2-catalin.marinas@xxxxxxx/ Unfortunately, this causes a duplicate definition warning for microblaze, powerpc (32-bit only) and sh as these architectures define ARCH_DMA_MINALIGN in a different file than asm/cache.h. Move the macro to asm/cache.h to avoid this issue and also bring them in line with the other architectures. This patch (of 3): The powerpc architecture defines ARCH_DMA_MINALIGN in asm/page_32.h and only if CONFIG_NOT_COHERENT_CACHE is enabled (32-bit platforms only). Move this macro to asm/cache.h to allow a generic ARCH_DMA_MINALIGN definition in linux/cache.h without redefine errors/warnings. Link: https://lkml.kernel.org/r/20230613155245.1228274-1-catalin.marinas@xxxxxxx Link: https://lkml.kernel.org/r/20230613155245.1228274-2-catalin.marinas@xxxxxxx Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx> Reported-by: kernel test robot <lkp@xxxxxxxxx> Closes: https://lore.kernel.org/oe-kbuild-all/202306131053.1ybvRRhO-lkp@xxxxxxxxx/ Cc: Michael Ellerman <mpe@xxxxxxxxxxxxxx> Cc: Nicholas Piggin <npiggin@xxxxxxxxx> Cc: Christophe Leroy <christophe.leroy@xxxxxxxxxx> Cc: John Paul Adrian Glaubitz <glaubitz@xxxxxxxxxxxxxxxxxxx> Cc: Michal Simek <monstr@xxxxxxxxx> Cc: Rich Felker <dalias@xxxxxxxx> Cc: Vlastimil Babka <vbabka@xxxxxxx> Cc: Yoshinori Sato <ysato@xxxxxxxxxxxxxxxxxxxx> Signed-off-by: Andrew Morton <akpm@xxxxxxxxxxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/powerpc/include/asm/cache.h | 4 ++++ arch/powerpc/include/asm/page_32.h | 4 ---- 2 files changed, 4 insertions(+), 4 deletions(-) --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -33,6 +33,10 @@ #define IFETCH_ALIGN_BYTES (1 << IFETCH_ALIGN_SHIFT) +#ifdef CONFIG_NOT_COHERENT_CACHE +#define ARCH_DMA_MINALIGN L1_CACHE_BYTES +#endif + #if !defined(__ASSEMBLY__) #ifdef CONFIG_PPC64 --- a/arch/powerpc/include/asm/page_32.h +++ b/arch/powerpc/include/asm/page_32.h @@ -12,10 +12,6 @@ #define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32 -#ifdef CONFIG_NOT_COHERENT_CACHE -#define ARCH_DMA_MINALIGN L1_CACHE_BYTES -#endif - #if defined(CONFIG_PPC_256K_PAGES) || \ (defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)) #define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */ Patches currently in stable-queue which might be from catalin.marinas@xxxxxxx are queue-6.1/kselftest-arm64-don-t-leak-pipe-fds-in-pac.exec_sign.patch queue-6.1/arm64-ptrace-fix-partial-setregset-for-nt_arm_tagged_addr_ctrl.patch queue-6.1/dma-allow-dma_get_cache_alignment-to-be-overridden-by-the-arch-code.patch queue-6.1/perf-arm-smmuv3-fix-lockdep-assert-in-event_init.patch queue-6.1/perf-arm-cmn-ensure-port-and-device-id-bits-are-set-.patch queue-6.1/kasan-suppress-recursive-reports-for-hw_tags.patch queue-6.1/kselftest-arm64-mte-fix-printf-type-warnings-about-l.patch queue-6.1/kselftest-arm64-mte-fix-printf-type-warnings-about-_.patch queue-6.1/arm64-tls-fix-context-switching-of-tpidrro_el0-when-kpti-is-enabled.patch queue-6.1/acpi-arm64-adjust-error-handling-procedure-in-gtdt_p.patch queue-6.1/mm-slab-decouple-arch_kmalloc_minalign-from-arch_dma_minalign.patch queue-6.1/powerpc-move-the-arch_dma_minalign-definition-to-asm-cache.h.patch queue-6.1/arm64-fix-.data.rel.ro-size-assertion-when-config_lt.patch queue-6.1/arm64-smccc-remove-broken-support-for-smcccv1.3-sve-discard-hint.patch queue-6.1/arm64-ensure-bits-asid-are-masked-out-when-the-kernel-uses-8-bit-asids.patch
