Patch "perf/x86/amd: Warn only on new bits set" has been added to the 6.12-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    perf/x86/amd: Warn only on new bits set

to the 6.12-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     perf-x86-amd-warn-only-on-new-bits-set.patch
and it can be found in the queue-6.12 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 32147505c76fcd974a57ef42b7acd720bd2f88bd
Author: Breno Leitao <leitao@xxxxxxxxxx>
Date:   Tue Oct 1 07:10:19 2024 -0700

    perf/x86/amd: Warn only on new bits set
    
    [ Upstream commit de20037e1b3c2f2ca97b8c12b8c7bca8abd509a7 ]
    
    Warning at every leaking bits can cause a flood of message, triggering
    various stall-warning mechanisms to fire, including CSD locks, which
    makes the machine to be unusable.
    
    Track the bits that are being leaked, and only warn when a new bit is
    set.
    
    That said, this patch will help with the following issues:
    
    1) It will tell us which bits are being set, so, it is easy to
       communicate it back to vendor, and to do a root-cause analyzes.
    
    2) It avoid the machine to be unusable, because, worst case
       scenario, the user gets less than 60 WARNs (one per unhandled bit).
    
    Suggested-by: Paul E. McKenney <paulmck@xxxxxxxxxx>
    Signed-off-by: Breno Leitao <leitao@xxxxxxxxxx>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
    Reviewed-by: Sandipan Das <sandipan.das@xxxxxxx>
    Reviewed-by: Paul E. McKenney <paulmck@xxxxxxxxxx>
    Link: https://lkml.kernel.org/r/20241001141020.2620361-1-leitao@xxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 920e3a640cadd..b4a1a2576510e 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -943,11 +943,12 @@ static int amd_pmu_v2_snapshot_branch_stack(struct perf_branch_entry *entries, u
 static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
 {
 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+	static atomic64_t status_warned = ATOMIC64_INIT(0);
+	u64 reserved, status, mask, new_bits, prev_bits;
 	struct perf_sample_data data;
 	struct hw_perf_event *hwc;
 	struct perf_event *event;
 	int handled = 0, idx;
-	u64 reserved, status, mask;
 	bool pmu_enabled;
 
 	/*
@@ -1012,7 +1013,12 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs)
 	 * the corresponding PMCs are expected to be inactive according to the
 	 * active_mask
 	 */
-	WARN_ON(status > 0);
+	if (status > 0) {
+		prev_bits = atomic64_fetch_or(status, &status_warned);
+		// A new bit was set for the very first time.
+		new_bits = status & ~prev_bits;
+		WARN(new_bits, "New overflows for inactive PMCs: %llx\n", new_bits);
+	}
 
 	/* Clear overflow and freeze bits */
 	amd_pmu_ack_global_status(~status);