drm/amdgpu/hdp4.0: do a posting read when flushing HDP

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From: Alex Deucher <alexander.deucher@xxxxxxx>

commit c9b8dcabb52afe88413ff135a0953e3cc4128483 upstream.

Need to read back to make sure the write goes through.

Cc: David Belanger <david.belanger@xxxxxxx>
Reviewed-by: Frank Min <frank.min@xxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
 drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c |   12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

--- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c
@@ -40,10 +40,12 @@
 static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev,
 				struct amdgpu_ring *ring)
 {
-	if (!ring || !ring->funcs->emit_wreg)
+	if (!ring || !ring->funcs->emit_wreg) {
 		WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
-	else
+		RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
+	} else {
 		amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
+	}
 }
 
 static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev,
@@ -54,11 +56,13 @@ static void hdp_v4_0_invalidate_hdp(stru
 	    amdgpu_ip_version(adev, HDP_HWIP, 0) == IP_VERSION(4, 4, 5))
 		return;
 
-	if (!ring || !ring->funcs->emit_wreg)
+	if (!ring || !ring->funcs->emit_wreg) {
 		WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
-	else
+		RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
+	} else {
 		amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 			HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
+	}
 }
 
 static void hdp_v4_0_query_ras_error_count(struct amdgpu_device *adev,


Patches currently in stable-queue which might be from alexander.deucher@xxxxxxx are

queue-6.12/drm-amdgpu-hdp4.0-do-a-posting-read-when-flushing-hdp.patch
queue-6.12/drm-amd-display-correct-prefetch-calculation.patch
queue-6.12/drm-amdkfd-add-mec-version-that-supports-no-pcie-atomics-for-gfx12.patch
queue-6.12/drm-amdkfd-hard-code-cacheline-for-gc943-gc944.patch
queue-6.12/drm-amdgpu-hdp5.2-do-a-posting-read-when-flushing-hdp.patch
queue-6.12/drm-amd-display-ignore-scalar-validation-failure-if-.patch
queue-6.12/drm-amdgpu-hdp5.0-do-a-posting-read-when-flushing-hdp.patch
queue-6.12/drm-amd-display-limit-vtotal-range-to-max-hw-cap-minus-fp.patch
queue-6.12/drm-amdgpu-rework-resume-handling-for-display-v2.patch
queue-6.12/drm-amd-display-calculate-final-viewport-before-tap-.patch
queue-6.12/drm-amd-display-add-a-left-edge-pixel-if-in-ycbcr422-or-ycbcr420-and-odm.patch
queue-6.12/drm-amdgpu-hdp6.0-do-a-posting-read-when-flushing-hdp.patch
queue-6.12/drm-amd-pm-fix-and-simplify-workload-handling.patch
queue-6.12/drm-amdgpu-hdp7.0-do-a-posting-read-when-flushing-hdp.patch




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