Patch "x86/CPU/AMD: WARN when setting EFER.AUTOIBRS if and only if the WRMSR fails" has been added to the 6.12-stable tree

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This is a note to let you know that I've just added the patch titled

    x86/CPU/AMD: WARN when setting EFER.AUTOIBRS if and only if the WRMSR fails

to the 6.12-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     x86-cpu-amd-warn-when-setting-efer.autoibrs-if-and-o.patch
and it can be found in the queue-6.12 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f78144a3627e3aabee0ea6b6d8b986a877300ec6
Author: Sean Christopherson <seanjc@xxxxxxxxxx>
Date:   Fri Dec 6 08:20:06 2024 -0800

    x86/CPU/AMD: WARN when setting EFER.AUTOIBRS if and only if the WRMSR fails
    
    [ Upstream commit 492077668fb453b8b16c842fcf3fafc2ebc190e9 ]
    
    When ensuring EFER.AUTOIBRS is set, WARN only on a negative return code
    from msr_set_bit(), as '1' is used to indicate the WRMSR was successful
    ('0' indicates the MSR bit was already set).
    
    Fixes: 8cc68c9c9e92 ("x86/CPU/AMD: Make sure EFER[AIBRSE] is set")
    Reported-by: Nathan Chancellor <nathan@xxxxxxxxxx>
    Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
    Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/Z1MkNofJjt7Oq0G6@xxxxxxxxxx
    Closes: https://lore.kernel.org/all/20241205220604.GA2054199@thelio-3990X
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index d8408aafeed98..79d2e17f6582e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -1065,7 +1065,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 	 */
 	if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) &&
 	    cpu_has(c, X86_FEATURE_AUTOIBRS))
-		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS));
+		WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS) < 0);
 
 	/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
 	clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);




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