Patch "clk: renesas: rzg2l: Fix FOUTPOSTDIV clk" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: renesas: rzg2l: Fix FOUTPOSTDIV clk

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-renesas-rzg2l-fix-foutpostdiv-clk.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 1c3f69ebbf2c297320544e6ddca7dc05d67026aa
Author: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Date:   Thu Oct 24 14:42:11 2024 +0100

    clk: renesas: rzg2l: Fix FOUTPOSTDIV clk
    
    [ Upstream commit dabf72b85f298970e86891b5218459c17b57b26a ]
    
    While computing foutpostdiv_rate, the value of params->pl5_fracin
    is discarded, which results in the wrong refresh rate. Fix the formula
    for computing foutpostdiv_rate.
    
    Fixes: 1561380ee72f ("clk: renesas: rzg2l: Add FOUTPOSTDIV clk support")
    Signed-off-by: Hien Huynh <hien.huynh.px@xxxxxxxxxxx>
    Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
    Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
    Link: https://lore.kernel.org/20241024134236.315289-1-biju.das.jz@xxxxxxxxxxxxxx
    Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 473feb36a38f2..5617040f307c4 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -289,7 +289,7 @@ static unsigned long
 rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params,
 			       unsigned long rate)
 {
-	unsigned long foutpostdiv_rate;
+	unsigned long foutpostdiv_rate, foutvco_rate;
 
 	params->pl5_intin = rate / MEGA;
 	params->pl5_fracin = div_u64(((u64)rate % MEGA) << 24, MEGA);
@@ -298,10 +298,11 @@ rzg2l_cpg_get_foutpostdiv_rate(struct rzg2l_pll5_param *params,
 	params->pl5_postdiv2 = 1;
 	params->pl5_spread = 0x16;
 
-	foutpostdiv_rate =
-		EXTAL_FREQ_IN_MEGA_HZ * MEGA / params->pl5_refdiv *
-		((((params->pl5_intin << 24) + params->pl5_fracin)) >> 24) /
-		(params->pl5_postdiv1 * params->pl5_postdiv2);
+	foutvco_rate = div_u64(mul_u32_u32(EXTAL_FREQ_IN_MEGA_HZ * MEGA,
+					   (params->pl5_intin << 24) + params->pl5_fracin),
+			       params->pl5_refdiv) >> 24;
+	foutpostdiv_rate = DIV_ROUND_CLOSEST_ULL(foutvco_rate,
+						 params->pl5_postdiv1 * params->pl5_postdiv2);
 
 	return foutpostdiv_rate;
 }




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