Patch "clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-ralink-mtmips-fix-clock-plan-for-ralink-soc-rt38.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 3a9fe71b81d863b2470f296bf4b53af6ff4f4608
Author: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
Date:   Tue Sep 10 06:40:22 2024 +0200

    clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
    
    [ Upstream commit 33239152305567b3e9bf052f71fd4baecd626341 ]
    
    Clock plan for Ralink SoC RT3883 needs an extra 'periph' clock to properly
    set some peripherals that has this clock as their parent. When this driver
    was mainlined we could not find any active users of this SoC so we cannot
    perform any real tests for it. Now, one user of a Belkin f9k1109 version 1
    device which uses this SoC appear and reported some issues in openWRT:
    - https://github.com/openwrt/openwrt/issues/16054
    The peripherals that are wrong are 'uart', 'i2c', 'i2s' and 'uartlite' which
    has a not defined 'periph' clock as parent. Hence, introduce it to have a
    properly working clock plan for this SoC.
    
    Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
    Signed-off-by: Sergio Paracuellos <sergio.paracuellos@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20240910044024.120009-2-sergio.paracuellos@xxxxxxxxx
    Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/ralink/clk-mtmips.c b/drivers/clk/ralink/clk-mtmips.c
index 50a443bf79ecd..62f9801ecd3a4 100644
--- a/drivers/clk/ralink/clk-mtmips.c
+++ b/drivers/clk/ralink/clk-mtmips.c
@@ -267,6 +267,11 @@ static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
 	CLK_FIXED("xtal", NULL, 40000000)
 };
 
+static struct mtmips_clk_fixed rt3883_fixed_clocks[] = {
+	CLK_FIXED("xtal", NULL, 40000000),
+	CLK_FIXED("periph", "xtal", 40000000)
+};
+
 static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
 	CLK_FIXED("periph", "xtal", 40000000)
 };
@@ -779,8 +784,8 @@ static const struct mtmips_clk_data rt3352_clk_data = {
 static const struct mtmips_clk_data rt3883_clk_data = {
 	.clk_base = rt3883_clks_base,
 	.num_clk_base = ARRAY_SIZE(rt3883_clks_base),
-	.clk_fixed = rt305x_fixed_clocks,
-	.num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
+	.clk_fixed = rt3883_fixed_clocks,
+	.num_clk_fixed = ARRAY_SIZE(rt3883_fixed_clocks),
 	.clk_factor = NULL,
 	.num_clk_factor = 0,
 	.clk_periph = rt5350_pherip_clks,




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