This is a note to let you know that I've just added the patch titled arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1 frequency to 506.8 MHz to the 6.11-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: arm64-dts-imx8mp-phyboard-pollux-set-video-pll1-freq.patch and it can be found in the queue-6.11 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. commit 9b8c8c3d96ef48769eb64d519bc56b6126bb4315 Author: Marek Vasut <marex@xxxxxxx> Date: Thu Oct 17 05:11:20 2024 +0200 arm64: dts: imx8mp-phyboard-pollux: Set Video PLL1 frequency to 506.8 MHz [ Upstream commit 4fbb73416b10778adfd2c1319e9c5829780d8535 ] The LVDS panel on this device uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout engine can reach accurate pixel clock of exactly 72.4 MHz. Without this patch, the Video PLL1 frequency is the default set in imx8mp.dtsi which is 1039.5 MHz, which divides down to inaccurate pixel clock of 74.25 MHz which works for this particular panel by sheer chance. Stop taking that chance and set correct accurate pixel clock frequency instead. Fixes: 326d86e197fc ("arm64: dts: imx8mp-phyboard-pollux-rdk: add etml panel support") Reported-by: Isaac Scott <isaac.scott@xxxxxxxxxxxxxxxx> Signed-off-by: Marek Vasut <marex@xxxxxxx> Reviewed-by: Yannic Moog <y.moog@xxxxxxxxx> Tested-by: Yannic Moog <y.moog@xxxxxxxxx> Signed-off-by: Shawn Guo <shawnguo@xxxxxxxxxx> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 00a240484c254..b6fd292a3b91d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -191,6 +191,18 @@ ldb_lvds_ch1: endpoint { }; }; +&media_blk_ctrl { + /* + * The LVDS panel on this device uses 72.4 MHz pixel clock, + * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB + * serializer and LCDIFv3 scanout engine can reach accurate + * pixel clock of exactly 72.4 MHz. + */ + assigned-clock-rates = <500000000>, <200000000>, + <0>, <0>, <500000000>, + <506800000>; +}; + &snvs_pwrkey { status = "okay"; };