From: Tejas Upadhyay <tejas.upadhyay@xxxxxxxxx>
commit f0ffa657e9f3913c7921cbd4d876343401f15f52 upstream.
Register GAMREQSTRM_CTRL should be considered mcr register
which should write to all slices as per documentation.
Bspec: 71185
Fixes: 01570b446939 ("drm/xe/bmg: implement Wa_16023588340")
Reviewed-by: Matt Roper <matthew.d.roper@xxxxxxxxx>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@xxxxxxxxx>
Link: https://patchwork.freedesktop.org/patch/msgid/20240814095614.909774-3-tejas.upadhyay@xxxxxxxxx
Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 +-
drivers/gpu/drm/xe/xe_gt.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -83,7 +83,7 @@
#define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148)
#define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0)
-#define XE2_GAMREQSTRM_CTRL XE_REG(0x4194)
+#define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194)
#define CG_DIS_CNTLBUS REG_BIT(6)
#define CCS_AUX_INV XE_REG(0x4208)
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -109,9 +109,9 @@ static void xe_gt_enable_host_l2_vram(st
if (!xe_gt_is_media_type(gt)) {
xe_mmio_write32(gt, SCRATCH1LPFC, EN_L3_RW_CCS_CACHE_FLUSH);
- reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
+ reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
reg |= CG_DIS_CNTLBUS;
- xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
+ xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
}
xe_gt_mcr_multicast_write(gt, XEHPC_L3CLOS_MASK(3), 0x3);
@@ -133,9 +133,9 @@ static void xe_gt_disable_host_l2_vram(s
if (WARN_ON(err))
return;
- reg = xe_mmio_read32(gt, XE2_GAMREQSTRM_CTRL);
+ reg = xe_gt_mcr_unicast_read_any(gt, XE2_GAMREQSTRM_CTRL);
reg &= ~CG_DIS_CNTLBUS;
- xe_mmio_write32(gt, XE2_GAMREQSTRM_CTRL, reg);
+ xe_gt_mcr_multicast_write(gt, XE2_GAMREQSTRM_CTRL, reg);
xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
}
Patches currently in stable-queue which might be from lucas.demarchi@xxxxxxxxx are
queue-6.11/drm-xe-add-mmio-read-before-ggtt-invalidate.patch
queue-6.11/drm-i915-disable-fbc-due-to-wa_16023588340.patch
queue-6.11/drm-i915-skip-programming-fia-link-enable-bits-for-mtl.patch
queue-6.11/drm-i915-display-cache-adpative-sync-caps-to-use-it-later.patch
queue-6.11/drm-i915-display-don-t-enable-decompression-on-xe2-with-tile4.patch
queue-6.11/drm-xe-xe2-introduce-performance-changes.patch
queue-6.11/drm-xe-define-stateless_compression_ctrl-as-mcr-register.patch
queue-6.11/drm-i915-hdcp-add-encoder-check-in-hdcp2_get_capability.patch
queue-6.11/drm-i915-hdcp-add-encoder-check-in-intel_hdcp_get_capability.patch
queue-6.11/drm-xe-don-t-short-circuit-tdr-on-jobs-not-started.patch
queue-6.11/drm-xe-write-all-slices-if-its-mcr-register.patch
queue-6.11/drm-i915-move-rawclk-from-runtime-to-display-runtime-info.patch
queue-6.11/drm-xe-display-drop-unused-rawclk_freq-and-runtime_info.patch
queue-6.11/drm-xe-xe2hpg-add-wa_15016589081.patch
queue-6.11/drm-i915-display-dp-compute-as-sdp-when-vrr-is-also-enabled.patch
queue-6.11/drm-i915-pps-disable-dpls_gating-around-pps-sequence.patch
queue-6.11/drm-i915-dp-clear-vsc-sdp-during-post-ddi-disable-routine.patch
queue-6.11/drm-xe-xe2-add-performance-turning-changes.patch
queue-6.11/drm-i915-psr-prevent-panel-replay-if-crc-calculation-is-enabled.patch
queue-6.11/drm-xe-move-enable-host-l2-vram-post-mcr-init.patch
queue-6.11/drm-xe-support-nomodeset-kernel-command-line-option.patch
queue-6.11/drm-xe-xe2hpg-introduce-performance-tuning-changes-for-xe2_hpg.patch
queue-6.11/drm-i915-display-wa-for-re-initialize-dispcnlunitt1-xosc-clock.patch
