On Fri, Oct 18, 2024 at 04:58:34PM +0200, Borislav Petkov wrote:
> On Fri, Oct 18, 2024 at 04:44:21PM +0200, gregkh@xxxxxxxxxxxxxxxxxxx wrote:
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -216,7 +216,7 @@
> > #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
> > #define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */
> > #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
> > -#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
> > +#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */
> > #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
> > #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */
> > #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
> > @@ -306,6 +306,7 @@
> > #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */
> > #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
> > #define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
> > +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* IBPB clears return address predictor */
>
> Right, so in all kernels before 6.11 that line should be
>
> +#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* "" IBPB clears return address predictor */
>
> note the "" in the comment - it is magical - because otherwise you'll start
> getting "amd_ibpb_ret" in /proc/cpuinfo and we don't necessarily want that.
>
> The commit that changed the logic is:
>
> 78ce84b9e0a5 ("x86/cpufeatures: Flip the /proc/cpuinfo appearance logic")
>
> and is in 6.11.
Ah, that's not obvious at all, magic comment fields :(
I'll go fix that up tomorrow, it's dinner time for now...
thanks,
greg k-h
