From: Easwar Hariharan <eahariha@xxxxxxxxxxxxxxxxxxx>
commit 3eddb108abe3de6723cc4b77e8558ce1b3047987 upstream.
Add the Microsoft Azure Cobalt 100 CPU to the list of CPUs suffering
from erratum 3194386 added in commit 75b3c43eab59 ("arm64: errata:
Expand speculative SSBS workaround")
CC: Mark Rutland <mark.rutland@xxxxxxx>
CC: James More <james.morse@xxxxxxx>
CC: Will Deacon <will@xxxxxxxxxx>
CC: stable@xxxxxxxxxxxxxxx # 6.6+
Signed-off-by: Easwar Hariharan <eahariha@xxxxxxxxxxxxxxxxxxx>
Link: https://lore.kernel.org/r/20241003225239.321774-1-eahariha@xxxxxxxxxxxxxxxxxxx
Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
Documentation/arch/arm64/silicon-errata.rst | 2 ++
arch/arm64/kernel/cpu_errata.c | 1 +
2 files changed, 3 insertions(+)
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -289,3 +289,5 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Microsoft | Azure Cobalt 100| #2253138 | ARM64_ERRATUM_2253138 |
+----------------+-----------------+-----------------+-----------------------------+
+| Microsoft | Azure Cobalt 100| #3324339 | ARM64_ERRATUM_3194386 |
++----------------+-----------------+-----------------+-----------------------------+
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -447,6 +447,7 @@ static const struct midr_range erratum_s
MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
+ MIDR_ALL_VERSIONS(MIDR_MICROSOFT_AZURE_COBALT_100),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
Patches currently in stable-queue which might be from eahariha@xxxxxxxxxxxxxxxxxxx are
queue-6.11/arm64-subscribe-microsoft-azure-cobalt-100-to-erratum-3194386.patch
