Patch "iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux" has been added to the 5.10-stable tree

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This is a note to let you know that I've just added the patch titled

    iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux

to the 5.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     iommu-arm-smmu-qcom-hide-last-lpass-smmu-context-ban.patch
and it can be found in the queue-5.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 663d1ecce9097a70bda8b98155d48d165e2c4c66
Author: Marc Gonzalez <mgonzalez@xxxxxxxxxx>
Date:   Tue Aug 20 15:27:19 2024 +0200

    iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux
    
    [ Upstream commit 3a8990b8a778219327c5f8ecf10b5d81377b925a ]
    
    On qcom msm8998, writing to the last context bank of lpass_q6_smmu
    (base address 0x05100000) produces a system freeze & reboot.
    
    The hardware/hypervisor reports 13 context banks for the LPASS SMMU
    on msm8998, but only the first 12 are accessible...
    Override the number of context banks
    
    [    2.546101] arm-smmu 5100000.iommu: probing hardware configuration...
    [    2.552439] arm-smmu 5100000.iommu: SMMUv2 with:
    [    2.558945] arm-smmu 5100000.iommu:  stage 1 translation
    [    2.563627] arm-smmu 5100000.iommu:  address translation ops
    [    2.568923] arm-smmu 5100000.iommu:  non-coherent table walk
    [    2.574566] arm-smmu 5100000.iommu:  (IDR0.CTTW overridden by FW configuration)
    [    2.580220] arm-smmu 5100000.iommu:  stream matching with 12 register groups
    [    2.587263] arm-smmu 5100000.iommu:  13 context banks (0 stage-2 only)
    [    2.614447] arm-smmu 5100000.iommu:  Supported page sizes: 0x63315000
    [    2.621358] arm-smmu 5100000.iommu:  Stage-1: 36-bit VA -> 36-bit IPA
    [    2.627772] arm-smmu 5100000.iommu:  preserved 0 boot mappings
    
    Specifically, the crashes occur here:
    
            qsmmu->bypass_cbndx = smmu->num_context_banks - 1;
            arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0);
    
    and here:
    
            arm_smmu_write_context_bank(smmu, i);
            arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
    
    It is likely that FW reserves the last context bank for its own use,
    thus a simple work-around is: DON'T USE IT in Linux.
    
    If we decrease the number of context banks, last one will be "hidden".
    
    Signed-off-by: Marc Gonzalez <mgonzalez@xxxxxxxxxx>
    Reviewed-by: Caleb Connolly <caleb.connolly@xxxxxxxxxx>
    Reviewed-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240820-smmu-v3-1-2f71483b00ec@xxxxxxxxxx
    Signed-off-by: Will Deacon <will@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index a5164d5cb6a35..91d9c4d98f39b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -39,6 +39,13 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu)
 	u32 smr;
 	int i;
 
+	/*
+	 * MSM8998 LPASS SMMU reports 13 context banks, but accessing
+	 * the last context bank crashes the system.
+	 */
+	if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") && smmu->num_context_banks == 13)
+		smmu->num_context_banks = 12;
+
 	/*
 	 * Some platforms support more than the Arm SMMU architected maximum of
 	 * 128 stream matching groups. For unknown reasons, the additional




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