Patch "x86/bugs: Add missing NO_SSB flag" has been added to the 6.10-stable tree

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This is a note to let you know that I've just added the patch titled

    x86/bugs: Add missing NO_SSB flag

to the 6.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     x86-bugs-add-missing-no_ssb-flag.patch
and it can be found in the queue-6.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 1247c64e6d9c800b7749ed463d0d5fcb8b11d2b5
Author: Daniel Sneddon <daniel.sneddon@xxxxxxxxxxxxxxx>
Date:   Thu Aug 29 12:24:37 2024 -0700

    x86/bugs: Add missing NO_SSB flag
    
    [ Upstream commit 23e12b54acf621f4f03381dca91cc5f1334f21fd ]
    
    The Moorefield and Lightning Mountain Atom processors are
    missing the NO_SSB flag in the vulnerabilities whitelist.
    This will cause unaffected parts to incorrectly be reported
    as vulnerable. Add the missing flag.
    
    These parts are currently out of service and were verified
    internally with archived documentation that they need the
    NO_SSB flag.
    
    Closes: https://lore.kernel.org/lkml/CAEJ9NQdhh+4GxrtG1DuYgqYhvc0hi-sKZh-2niukJ-MyFLntAA@xxxxxxxxxxxxxx/
    Reported-by: Shanavas.K.S <shanavasks@xxxxxxxxx>
    Signed-off-by: Daniel Sneddon <daniel.sneddon@xxxxxxxxxxxxxxx>
    Signed-off-by: Borislav Petkov (AMD) <bp@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20240829192437.4074196-1-daniel.sneddon@xxxxxxxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index d4e539d4e158c..be307c9ef263d 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1165,8 +1165,8 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 
 	VULNWL_INTEL(INTEL_CORE_YONAH,		NO_SSB),
 
-	VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID,	NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
-	VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP,	NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
+	VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID,	NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
+	VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP,	NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
 
 	VULNWL_INTEL(INTEL_ATOM_GOLDMONT,	NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
 	VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D,	NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),




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