Patch "clk: imx: imx8mp: fix clock tree update of TF-A managed clocks" has been added to the 6.6-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    clk: imx: imx8mp: fix clock tree update of TF-A managed clocks

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-imx-imx8mp-fix-clock-tree-update-of-tf-a-managed.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 7fd8164c31877f54f8b37193bbf91250fa327de8
Author: Zhipeng Wang <zhipeng.wang_1@xxxxxxx>
Date:   Fri Jun 7 21:33:38 2024 +0800

    clk: imx: imx8mp: fix clock tree update of TF-A managed clocks
    
    [ Upstream commit 3d29036853b9cb07ac49e8261fca82a940be5c41 ]
    
    On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service
    for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the
    SiP and then does clk_set_parent on the DDR muxes to synchronize
    the clock tree.
    
    since commit 936c383673b9 ("clk: imx: fix composite peripheral flags"),
    these TF-A managed muxes have SET_PARENT_GATE set, which results
    in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:
    
    clk_set_parent(dram_apb_src, sys1_pll_40m);(busfreq-imx8mq.c)
    
    commit 926bf91248dd
    ("clk: imx8m: fix clock tree update of TF-A managed clocks") adds this
    method and enables 8mm, 8mn and 8mq. i.MX8MP also needs it.
    
    This is safe to do, because updating the Linux clock tree to reflect
    reality will always be glitch-free.
    
    Another reason to this patch is that powersave image BT music
    requires dram to be 400MTS, so clk_set_parent(dram_alt_src,
    sys1_pll_800m); is required. Without this patch, it will not succeed.
    
    Fixes: 936c383673b9 ("clk: imx: fix composite peripheral flags")
    Signed-off-by: Zhipeng Wang <zhipeng.wang_1@xxxxxxx>
    Reviewed-by: Ahmad Fatoum <a.fatoum@xxxxxxxxxxxxxx>
    Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
    Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240607133347.3291040-7-peng.fan@xxxxxxxxxxx
    Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 670aa2bab3017..e561ff7b135fb 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -551,8 +551,8 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
 
 	hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
 
-	hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
-	hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
+	hws[IMX8MP_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000);
+	hws[IMX8MP_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080);
 	hws[IMX8MP_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100);
 	hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180);
 	hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200);