Patch "clk: imx: composite-7ulp: Check the PCC present bit" has been added to the 6.6-stable tree

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



This is a note to let you know that I've just added the patch titled

    clk: imx: composite-7ulp: Check the PCC present bit

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-imx-composite-7ulp-check-the-pcc-present-bit.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 8e31b73597a5cc7069ea9a570969a61e74dbed38
Author: Ye Li <ye.li@xxxxxxx>
Date:   Fri Jun 7 21:33:35 2024 +0800

    clk: imx: composite-7ulp: Check the PCC present bit
    
    [ Upstream commit 4717ccadb51e2630790dddd222830702de17f090 ]
    
    When some module is disabled by fuse, its PCC PR bit is default 0 and
    PCC is not operational. Any write to this PCC will cause SError.
    
    Fixes: b40ba8065347 ("clk: imx: Update the compsite driver to support imx8ulp")
    Reviewed-by: Peng Fan <peng.fan@xxxxxxx>
    Signed-off-by: Ye Li <ye.li@xxxxxxx>
    Signed-off-by: Peng Fan <peng.fan@xxxxxxx>
    Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240607133347.3291040-4-peng.fan@xxxxxxxxxxx
    Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/imx/clk-composite-7ulp.c b/drivers/clk/imx/clk-composite-7ulp.c
index e208ddc511339..db7f40b07d1ab 100644
--- a/drivers/clk/imx/clk-composite-7ulp.c
+++ b/drivers/clk/imx/clk-composite-7ulp.c
@@ -14,6 +14,7 @@
 #include "../clk-fractional-divider.h"
 #include "clk.h"
 
+#define PCG_PR_MASK		BIT(31)
 #define PCG_PCS_SHIFT	24
 #define PCG_PCS_MASK	0x7
 #define PCG_CGC_SHIFT	30
@@ -78,6 +79,12 @@ static struct clk_hw *imx_ulp_clk_hw_composite(const char *name,
 	struct clk_hw *hw;
 	u32 val;
 
+	val = readl(reg);
+	if (!(val & PCG_PR_MASK)) {
+		pr_info("PCC PR is 0 for clk:%s, bypass\n", name);
+		return 0;
+	}
+
 	if (mux_present) {
 		mux = kzalloc(sizeof(*mux), GFP_KERNEL);
 		if (!mux)




[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Index of Archives]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux