Patch "clk: qcom: dispcc-sm8550: fix several supposed typos" has been added to the 6.10-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: qcom: dispcc-sm8550: fix several supposed typos

to the 6.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-dispcc-sm8550-fix-several-supposed-typos.patch
and it can be found in the queue-6.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 74478936cd0077b3af20ad902d5b0983a2a05320
Author: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Date:   Wed Jul 17 13:04:28 2024 +0300

    clk: qcom: dispcc-sm8550: fix several supposed typos
    
    [ Upstream commit 7b6a4b907297b28727933493b9e0c95494504634 ]
    
    Fix seveal odd-looking places in SM8550's dispcc driver:
    
    - duplicate entries in disp_cc_parent_map_4 and disp_cc_parent_map_5
    - using &disp_cc_mdss_dptx0_link_div_clk_src as a source for
      disp_cc_mdss_dptx1_usb_router_link_intf_clk
    
    The SM8650 driver has been used as a reference.
    
    Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver")
    Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
    Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-1-5c4a3128c40b@xxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/dispcc-sm8550.c b/drivers/clk/qcom/dispcc-sm8550.c
index 38ecea805503d..56918e2a7734d 100644
--- a/drivers/clk/qcom/dispcc-sm8550.c
+++ b/drivers/clk/qcom/dispcc-sm8550.c
@@ -196,7 +196,7 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
 static const struct parent_map disp_cc_parent_map_4[] = {
 	{ P_BI_TCXO, 0 },
 	{ P_DP0_PHY_PLL_LINK_CLK, 1 },
-	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 2 },
+	{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
 	{ P_DP3_PHY_PLL_VCO_DIV_CLK, 3 },
 	{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
 	{ P_DP2_PHY_PLL_VCO_DIV_CLK, 6 },
@@ -213,7 +213,7 @@ static const struct clk_parent_data disp_cc_parent_data_4[] = {
 
 static const struct parent_map disp_cc_parent_map_5[] = {
 	{ P_BI_TCXO, 0 },
-	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 4 },
+	{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
 	{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
 };
 




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