Patch "arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*" has been added to the 6.10-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*

to the 6.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-mediatek-mt8195-correct-clock-order-for-dp.patch
and it can be found in the queue-6.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 5a5c4f935260256d05e206f632f70c27e4d57d17
Author: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
Date:   Fri Aug 2 15:09:50 2024 +0800

    arm64: dts: mediatek: mt8195: Correct clock order for dp_intf*
    
    [ Upstream commit 51bc68debab9e30b50c6352315950f3cfc309b32 ]
    
    The clocks for dp_intf* device nodes are given in the wrong order,
    causing the binding validation to fail.
    
    Fixes: 6c2503b5856a ("arm64: dts: mt8195: Add dp-intf nodes")
    Signed-off-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
    Reviewed-by: Nícolas F. R. A. Prado <nfraprado@xxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240802070951.1086616-1-wenst@xxxxxxxxxxxx
    Signed-off-by: Matthias Brugger <matthias.bgg@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 2ee45752583c0..98c15eb68589a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -3251,10 +3251,10 @@ dp_intf0: dp-intf@1c015000 {
 			compatible = "mediatek,mt8195-dp-intf";
 			reg = <0 0x1c015000 0 0x1000>;
 			interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
-			clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
-				 <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+			clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+				 <&vdosys0  CLK_VDO0_DP_INTF0>,
 				 <&apmixedsys CLK_APMIXED_TVDPLL1>;
-			clock-names = "engine", "pixel", "pll";
+			clock-names = "pixel", "engine", "pll";
 			status = "disabled";
 		};
 
@@ -3521,10 +3521,10 @@ dp_intf1: dp-intf@1c113000 {
 			reg = <0 0x1c113000 0 0x1000>;
 			interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
-			clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
-				 <&vdosys1 CLK_VDO1_DPINTF>,
+			clocks = <&vdosys1 CLK_VDO1_DPINTF>,
+				 <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
 				 <&apmixedsys CLK_APMIXED_TVDPLL2>;
-			clock-names = "engine", "pixel", "pll";
+			clock-names = "pixel", "engine", "pll";
 			status = "disabled";
 		};