From: Vijendar Mukunda <Vijendar.Mukunda@xxxxxxx> commit c35fad6f7e0d69b0e9e7e196bdbca3ed03ac24ea upstream. Add ZSC Control register programming sequence for ACP D0 and D3 state transitions for ACP7.0 onwards. This will allow ACP to enter low power state when ACP enters D3 state. When ACP enters D0 State, ZSC control should be disabled. Tested-by: Leo Li <sunpeng.li@xxxxxxx> Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@xxxxxxx> Link: https://patch.msgid.link/20240807085154.1987681-1-Vijendar.Mukunda@xxxxxxx Signed-off-by: Mark Brown <broonie@xxxxxxxxxx> Cc: Mario Limonciello <mario.limonciello@xxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- sound/soc/amd/acp/acp-legacy-common.c | 5 +++++ sound/soc/amd/acp/amd.h | 2 ++ 2 files changed, 7 insertions(+) --- a/sound/soc/amd/acp/acp-legacy-common.c +++ b/sound/soc/amd/acp/acp-legacy-common.c @@ -321,6 +321,8 @@ int acp_init(struct acp_chip_info *chip) pr_err("ACP reset failed\n"); return ret; } + if (chip->acp_rev >= ACP70_DEV) + writel(0, chip->base + ACP_ZSC_DSP_CTRL); return 0; } EXPORT_SYMBOL_NS_GPL(acp_init, SND_SOC_ACP_COMMON); @@ -336,6 +338,9 @@ int acp_deinit(struct acp_chip_info *chi if (chip->acp_rev != ACP70_DEV) writel(0, chip->base + ACP_CONTROL); + + if (chip->acp_rev >= ACP70_DEV) + writel(0x01, chip->base + ACP_ZSC_DSP_CTRL); return 0; } EXPORT_SYMBOL_NS_GPL(acp_deinit, SND_SOC_ACP_COMMON); --- a/sound/soc/amd/acp/amd.h +++ b/sound/soc/amd/acp/amd.h @@ -103,6 +103,8 @@ #define ACP70_PGFSM_CONTROL ACP6X_PGFSM_CONTROL #define ACP70_PGFSM_STATUS ACP6X_PGFSM_STATUS +#define ACP_ZSC_DSP_CTRL 0x0001014 +#define ACP_ZSC_STS 0x0001018 #define ACP_SOFT_RST_DONE_MASK 0x00010001 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0xffffffff Patches currently in stable-queue which might be from Vijendar.Mukunda@xxxxxxx are queue-6.11/asoc-amd-acp-add-zsc-control-register-programming-sequence.patch
