Patch "drm/amd/display: Check num_valid_sets before accessing reader_wm_sets[]" has been added to the 6.10-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amd/display: Check num_valid_sets before accessing reader_wm_sets[]

to the 6.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-check-num_valid_sets-before-accessin.patch
and it can be found in the queue-6.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 115692fb6ed59e3d503eee30fc1448b57d23a959
Author: Alex Hung <alex.hung@xxxxxxx>
Date:   Tue Apr 16 16:22:35 2024 -0600

    drm/amd/display: Check num_valid_sets before accessing reader_wm_sets[]
    
    [ Upstream commit b38a4815f79b87efb196cd5121579fc51e29a7fb ]
    
    [WHY & HOW]
    num_valid_sets needs to be checked to avoid a negative index when
    accessing reader_wm_sets[num_valid_sets - 1].
    
    This fixes an OVERRUN issue reported by Coverity.
    
    Reviewed-by: Harry Wentland <harry.wentland@xxxxxxx>
    Acked-by: Tom Chung <chiahsuan.chung@xxxxxxx>
    Signed-off-by: Alex Hung <alex.hung@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 5ef0879f6ad9..aea4bb46856e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -484,7 +484,8 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm
 			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 
 			/* Modify previous watermark range to cover up to max */
-			ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
+			if (num_valid_sets > 0)
+				ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 		}
 		num_valid_sets++;
 	}




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