Patch "irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same time" has been added to the 6.1-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same time

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     irqchip-renesas-rzg2l-do-not-set-tien-and-tint-sourc.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 502f75b4c232807166c52d5319c0b81645fb062f
Author: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Date:   Mon Mar 18 08:50:40 2024 +0000

    irqchip/renesas-rzg2l: Do not set TIEN and TINT source at the same time
    
    [ Upstream commit dce0919c83c325ac9dec5bc8838d5de6d32c01b1 ]
    
    As per the hardware team, TIEN and TINT source should not set at the same
    time due to a possible hardware race leading to spurious IRQ.
    
    Currently on some scenarios hardware settings for TINT detection is not in
    sync with TINT source as the enable/disable overrides source setting value
    leading to hardware inconsistent state. For eg: consider the case GPIOINT0
    is used as TINT interrupt and configuring GPIOINT5 as edge type. During
    rzg2l_irq_set_type(), TINT source for GPIOINT5 is set. On disable(),
    clearing of the entire bytes of TINT source selection for GPIOINT5 is same
    as GPIOINT0 with TIEN disabled. Apart from this during enable(), the
    setting of GPIOINT5 with TIEN results in spurious IRQ as due to a HW race,
    it is possible that IP can use the TIEN with previous source value
    (GPIOINT0).
    
    So, just update TIEN during enable/disable as TINT source is already set
    during rzg2l_irq_set_type(). This will make the consistent hardware
    settings for detection method tied with TINT source and allows to simplify
    the code.
    
    Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
    Signed-off-by: Thomas Gleixner <tglx@xxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index be71459c7465a..70279ca7e6278 100644
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -132,7 +132,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d)
 
 		raw_spin_lock(&priv->lock);
 		reg = readl_relaxed(priv->base + TSSR(tssr_index));
-		reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
+		reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
 		writel_relaxed(reg, priv->base + TSSR(tssr_index));
 		raw_spin_unlock(&priv->lock);
 	}
@@ -145,7 +145,6 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d)
 
 	if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
 		struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
-		unsigned long tint = (uintptr_t)d->chip_data;
 		u32 offset = hw_irq - IRQC_TINT_START;
 		u32 tssr_offset = TSSR_OFFSET(offset);
 		u8 tssr_index = TSSR_INDEX(offset);
@@ -153,7 +152,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d)
 
 		raw_spin_lock(&priv->lock);
 		reg = readl_relaxed(priv->base + TSSR(tssr_index));
-		reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset);
+		reg |= TIEN << TSSEL_SHIFT(tssr_offset);
 		writel_relaxed(reg, priv->base + TSSR(tssr_index));
 		raw_spin_unlock(&priv->lock);
 	}