Patch "arm64: cputype: Add Cortex-X925 definitions" has been added to the 5.4-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: cputype: Add Cortex-X925 definitions

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-cputype-add-cortex-x925-definitions.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit c9427c8bae797ff27e9937fa55fee4d147c2be21
Author: Mark Rutland <mark.rutland@xxxxxxx>
Date:   Fri Aug 9 11:34:21 2024 +0100

    arm64: cputype: Add Cortex-X925 definitions
    
    [ Upstream commit fd2ff5f0b320f418288e7a1f919f648fbc8a0dfc ]
    
    Add cputype definitions for Cortex-X925. These will be used for errata
    detection in subsequent patches.
    
    These values can be found in Table A-285 ("MIDR_EL1 bit descriptions")
    in issue 0001-05 of the Cortex-X925 TRM, which can be found at:
    
      https://developer.arm.com/documentation/102807/0001/?lang=en
    
    Signed-off-by: Mark Rutland <mark.rutland@xxxxxxx>
    Cc: James Morse <james.morse@xxxxxxx>
    Cc: Will Deacon <will@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240603111812.1514101-4-mark.rutland@xxxxxxx
    Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
    [ Mark: trivial backport ]
    Signed-off-by: Mark Rutland <mark.rutland@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 540c25014c9de..6322263063887 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -85,6 +85,7 @@
 #define ARM_CPU_PART_CORTEX_A720	0xD81
 #define ARM_CPU_PART_CORTEX_X4		0xD82
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
+#define ARM_CPU_PART_CORTEX_X925	0xD85
 
 #define APM_CPU_PART_POTENZA		0x000
 
@@ -131,6 +132,7 @@
 #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
 #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
+#define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)




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