Patch "arm64: cputype: Add Cortex-X3 definitions" has been added to the 5.4-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: cputype: Add Cortex-X3 definitions

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-cputype-add-cortex-x3-definitions.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 59e84e32b1a0e00388ecdfe11df5348f81f54f1b
Author: Mark Rutland <mark.rutland@xxxxxxx>
Date:   Fri Aug 9 11:34:19 2024 +0100

    arm64: cputype: Add Cortex-X3 definitions
    
    [ Upstream commit be5a6f238700f38b534456608588723fba96c5ab ]
    
    Add cputype definitions for Cortex-X3. These will be used for errata
    detection in subsequent patches.
    
    These values can be found in Table A-263 ("MIDR_EL1 bit descriptions")
    in issue 07 of the Cortex-X3 TRM, which can be found at:
    
      https://developer.arm.com/documentation/101593/0102/?lang=en
    
    Signed-off-by: Mark Rutland <mark.rutland@xxxxxxx>
    Cc: James Morse <james.morse@xxxxxxx>
    Cc: Will Deacon <will@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240603111812.1514101-2-mark.rutland@xxxxxxx
    Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
    [ Mark: trivial backport ]
    Signed-off-by: Mark Rutland <mark.rutland@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 0c3f9cc84491c..4b27bfc0d8569 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -80,6 +80,7 @@
 #define ARM_CPU_PART_CORTEX_X2		0xD48
 #define ARM_CPU_PART_NEOVERSE_N2	0xD49
 #define ARM_CPU_PART_CORTEX_A78C	0xD4B
+#define ARM_CPU_PART_CORTEX_X3		0xD4E
 #define ARM_CPU_PART_NEOVERSE_V2	0xD4F
 #define ARM_CPU_PART_CORTEX_X4		0xD82
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
@@ -124,6 +125,7 @@
 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
 #define MIDR_CORTEX_A78C	MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
+#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
 #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
 #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)




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