Patch "arm64: cputype: Add Cortex-A725 definitions" has been added to the 6.10-stable tree

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This is a note to let you know that I've just added the patch titled

    arm64: cputype: Add Cortex-A725 definitions

to the 6.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-cputype-add-cortex-a725-definitions.patch
and it can be found in the queue-6.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 068a38c14e0f5dda0f61939fc51fd3629e21bd84
Author: Mark Rutland <mark.rutland@xxxxxxx>
Date:   Fri Aug 9 10:51:19 2024 +0100

    arm64: cputype: Add Cortex-A725 definitions
    
    [ Upstream commit 9ef54a384526911095db465e77acc1cb5266b32c ]
    
    Add cputype definitions for Cortex-A725. These will be used for errata
    detection in subsequent patches.
    
    These values can be found in the Cortex-A725 TRM:
    
      https://developer.arm.com/documentation/107652/0001/
    
    ... in table A-247 ("MIDR_EL1 bit descriptions").
    
    Signed-off-by: Mark Rutland <mark.rutland@xxxxxxx>
    Cc: James Morse <james.morse@xxxxxxx>
    Cc: Will Deacon <will@xxxxxxxxxx>
    Reviewed-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
    Link: https://lore.kernel.org/r/20240801101803.1982459-3-mark.rutland@xxxxxxx
    Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
    [ Mark: trivial backport ]
    Signed-off-by: Mark Rutland <mark.rutland@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 5dc68ace305e5..5fd7caea44193 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -93,6 +93,7 @@
 #define ARM_CPU_PART_CORTEX_X4		0xD82
 #define ARM_CPU_PART_NEOVERSE_V3	0xD84
 #define ARM_CPU_PART_CORTEX_X925	0xD85
+#define ARM_CPU_PART_CORTEX_A725	0xD87
 
 #define APM_CPU_PART_XGENE		0x000
 #define APM_CPU_VAR_POTENZA		0x00
@@ -173,6 +174,7 @@
 #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
+#define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
 #define MIDR_THUNDERX	MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)




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