Patch "perf/x86: Fix smp_processor_id()-in-preemptible warnings" has been added to the 6.10-stable tree

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This is a note to let you know that I've just added the patch titled

    perf/x86: Fix smp_processor_id()-in-preemptible warnings

to the 6.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     perf-x86-fix-smp_processor_id-in-preemptible-warning.patch
and it can be found in the queue-6.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit ade587b6d2d92bc9bed6cb7147eb464f4066b969
Author: Li Huafei <lihuafei1@xxxxxxxxxx>
Date:   Tue Jul 30 06:09:28 2024 +0800

    perf/x86: Fix smp_processor_id()-in-preemptible warnings
    
    [ Upstream commit f73cefa3b72eaa90abfc43bf6d68137ba059d4b1 ]
    
    The following bug was triggered on a system built with
    CONFIG_DEBUG_PREEMPT=y:
    
     # echo p > /proc/sysrq-trigger
    
     BUG: using smp_processor_id() in preemptible [00000000] code: sh/117
     caller is perf_event_print_debug+0x1a/0x4c0
     CPU: 3 UID: 0 PID: 117 Comm: sh Not tainted 6.11.0-rc1 #109
     Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.13.0-1ubuntu1.1 04/01/2014
     Call Trace:
      <TASK>
      dump_stack_lvl+0x4f/0x60
      check_preemption_disabled+0xc8/0xd0
      perf_event_print_debug+0x1a/0x4c0
      __handle_sysrq+0x140/0x180
      write_sysrq_trigger+0x61/0x70
      proc_reg_write+0x4e/0x70
      vfs_write+0xd0/0x430
      ? handle_mm_fault+0xc8/0x240
      ksys_write+0x9c/0xd0
      do_syscall_64+0x96/0x190
      entry_SYSCALL_64_after_hwframe+0x4b/0x53
    
    This is because the commit d4b294bf84db ("perf/x86: Hybrid PMU support
    for counters") took smp_processor_id() outside the irq critical section.
    If a preemption occurs in perf_event_print_debug() and the task is
    migrated to another cpu, we may get incorrect pmu debug information.
    Move smp_processor_id() back inside the irq critical section to fix this
    issue.
    
    Fixes: d4b294bf84db ("perf/x86: Hybrid PMU support for counters")
    Signed-off-by: Li Huafei <lihuafei1@xxxxxxxxxx>
    Reviewed-and-tested-by: K Prateek Nayak <kprateek.nayak@xxxxxxx>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@xxxxxxxxxxxxx>
    Reviewed-by: Kan Liang <kan.liang@xxxxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240729220928.325449-1-lihuafei1@xxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 0c51cfdf76092..83d12dd3f831a 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -1521,20 +1521,23 @@ static void x86_pmu_start(struct perf_event *event, int flags)
 void perf_event_print_debug(void)
 {
 	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
+	unsigned long *cntr_mask, *fixed_cntr_mask;
+	struct event_constraint *pebs_constraints;
+	struct cpu_hw_events *cpuc;
 	u64 pebs, debugctl;
-	int cpu = smp_processor_id();
-	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
-	unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask);
-	unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
-	struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
-	unsigned long flags;
-	int idx;
+	int cpu, idx;
+
+	guard(irqsave)();
+
+	cpu = smp_processor_id();
+	cpuc = &per_cpu(cpu_hw_events, cpu);
+	cntr_mask = hybrid(cpuc->pmu, cntr_mask);
+	fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask);
+	pebs_constraints = hybrid(cpuc->pmu, pebs_constraints);
 
 	if (!*(u64 *)cntr_mask)
 		return;
 
-	local_irq_save(flags);
-
 	if (x86_pmu.version >= 2) {
 		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
@@ -1578,7 +1581,6 @@ void perf_event_print_debug(void)
 		pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
 			cpu, idx, pmc_count);
 	}
-	local_irq_restore(flags);
 }
 
 void x86_pmu_stop(struct perf_event *event, int flags)




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