Patch "ARM: dts: imx6qdl-kontron-samx6i: fix PHY reset" has been added to the 5.4-stable tree

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This is a note to let you know that I've just added the patch titled

    ARM: dts: imx6qdl-kontron-samx6i: fix PHY reset

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm-dts-imx6qdl-kontron-samx6i-fix-phy-reset.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 139666b7e0babf5689e92cf90bb266baf16c481c
Author: Michael Walle <mwalle@xxxxxxxxxx>
Date:   Mon Jun 17 11:13:30 2024 +0200

    ARM: dts: imx6qdl-kontron-samx6i: fix PHY reset
    
    [ Upstream commit edfea889a049abe80f0d55c0365bf60fbade272f ]
    
    The PHY reset line is connected to both the SoC (GPIO1_25) and
    the CPLD. We must not use the GPIO1_25 as it will drive against
    the output buffer of the CPLD. Instead there is another GPIO
    (GPIO2_01), an input to the CPLD, which will tell the CPLD to
    assert the PHY reset line.
    
    Fixes: 2a51f9dae13d ("ARM: dts: imx6qdl-kontron-samx6i: Add iMX6-based Kontron SMARC-sAMX6i module")
    Fixes: 5694eed98cca ("ARM: dts: imx6qdl-kontron-samx6i: move phy reset into phy-node")
    Signed-off-by: Michael Walle <mwalle@xxxxxxxxxx>
    Signed-off-by: Shawn Guo <shawnguo@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
index 1b9e38ec74489..1dcbad290cac0 100644
--- a/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-kontron-samx6i.dtsi
@@ -269,7 +269,7 @@ mdio {
 		ethphy: ethernet-phy@1 {
 			compatible = "ethernet-phy-ieee802.3-c22";
 			reg = <1>;
-			reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+			reset-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 		};
 	};
@@ -512,7 +512,7 @@ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b0b0 /* RST_GBE0_PHY# */
+			MX6QDL_PAD_NANDF_D1__GPIO2_IO01       0x1b0b0 /* RST_GBE0_PHY# */
 		>;
 	};
 




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