This is a note to let you know that I've just added the patch titled
arm64: dts: renesas: r8a779g0: Add L3 cache controller
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-dts-renesas-r8a779g0-add-l3-cache-controller.patch
and it can be found in the queue-6.1 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
commit b48f0d2c99d8f2f687700af468c9c00afa1247bb
Author: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Date: Mon Nov 14 13:49:00 2022 +0100
arm64: dts: renesas: r8a779g0: Add L3 cache controller
[ Upstream commit f08407210db921a4c9eaeaa92d0c434858b9c6c4 ]
Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.
Extracted from a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@xxxxxxxxx
Stable-dep-of: 6fca24a07e1d ("arm64: dts: renesas: r8a779a0: Add missing hypervisor virtual timer IRQ")
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
index 868d1a3cbdf61..9f6a30cf315f2 100644
--- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi
@@ -23,6 +23,14 @@ a76_0: cpu@0 {
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
+ next-level-cache = <&L3_CA76_0>;
+ };
+
+ L3_CA76_0: cache-controller-0 {
+ compatible = "cache";
+ power-domains = <&sysc R8A779G0_PD_A2E0D0>;
+ cache-unified;
+ cache-level = <3>;
};
};
