Patch "clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable" has been added to the 6.6-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-gpucc-sa8775p-park-rcg-s-clk-source-at-xo-d.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 3354014cd206579ab0d4d9c3a25912e060ae79b3
Author: Taniya Das <quic_tdas@xxxxxxxxxxx>
Date:   Wed Jun 12 16:38:25 2024 +0530

    clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable
    
    [ Upstream commit dff68b2f74547617dbb75d0d12f404877ec8f8ce ]
    
    The RCG's clk src has to be parked at XO while disabling as per the
    HW recommendation, hence use clk_rcg2_shared_ops to achieve the same.
    Also gpu_cc_cb_clk is recommended to be kept always ON, hence use
    clk_branch2_aon_ops to keep the clock always ON.
    
    Fixes: 0afa16afc36d ("clk: qcom: add the GPUCC driver for sa8775p")
    Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
    Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-5-adcc756a23df@xxxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index 3f05b44c13c53..abcaefa01e386 100644
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -161,7 +161,7 @@ static struct clk_rcg2 gpu_cc_ff_clk_src = {
 		.name = "gpu_cc_ff_clk_src",
 		.parent_data = gpu_cc_parent_data_0,
 		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_rcg2_shared_ops,
 	},
 };
 
@@ -181,7 +181,7 @@ static struct clk_rcg2 gpu_cc_gmu_clk_src = {
 		.parent_data = gpu_cc_parent_data_1,
 		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
 		.flags = CLK_SET_RATE_PARENT,
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_rcg2_shared_ops,
 	},
 };
 
@@ -200,7 +200,7 @@ static struct clk_rcg2 gpu_cc_hub_clk_src = {
 		.name = "gpu_cc_hub_clk_src",
 		.parent_data = gpu_cc_parent_data_2,
 		.num_parents = ARRAY_SIZE(gpu_cc_parent_data_2),
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_rcg2_shared_ops,
 	},
 };
 
@@ -294,7 +294,7 @@ static struct clk_branch gpu_cc_cb_clk = {
 		.enable_mask = BIT(0),
 		.hw.init = &(const struct clk_init_data){
 			.name = "gpu_cc_cb_clk",
-			.ops = &clk_branch2_ops,
+			.ops = &clk_branch2_aon_ops,
 		},
 	},
 };