Patch "clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-gcc-sm6350-fix-gpll6-gpll7-parents.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 2411fb9f7750f1604fe8d9b297d1e6d802ad4982
Author: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
Date:   Wed May 8 10:12:53 2024 +0200

    clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents
    
    [ Upstream commit 3414f41a13eb41db15c558fbc695466203dca4fa ]
    
    Both gpll6 and gpll7 are parented to CXO at 19.2 MHz and not to GPLL0
    which runs at 600 MHz. Also gpll6_out_even should have the parent gpll6
    and not gpll0.
    
    Adjust the parents of these clocks to make Linux report the correct rate
    and not absurd numbers like gpll7 at ~25 GHz or gpll6 at 24 GHz.
    
    Corrected rates are the following:
    
      gpll7              807999902 Hz
      gpll6              768000000 Hz
         gpll6_out_even  384000000 Hz
      gpll0              600000000 Hz
         gpll0_out_odd   200000000 Hz
         gpll0_out_even  300000000 Hz
    
    And because gpll6 is the parent of gcc_sdcc2_apps_clk_src (at 202 MHz)
    that clock also reports the correct rate now and avoids this warning:
    
      [    5.984062] mmc0: Card appears overclocked; req 202000000 Hz, actual 6312499237 Hz
    
    Fixes: 131abae905df ("clk: qcom: Add SM6350 GCC driver")
    Signed-off-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240508-sm6350-gpll-fix-v1-1-e4ea34284a6d@xxxxxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/gcc-sm6350.c b/drivers/clk/qcom/gcc-sm6350.c
index cf4a7b6e0b23a..0559a33faf00e 100644
--- a/drivers/clk/qcom/gcc-sm6350.c
+++ b/drivers/clk/qcom/gcc-sm6350.c
@@ -100,8 +100,8 @@ static struct clk_alpha_pll gpll6 = {
 		.enable_mask = BIT(6),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll6",
-			.parent_hws = (const struct clk_hw*[]){
-				&gpll0.clkr.hw,
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "bi_tcxo",
 			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fixed_fabia_ops,
@@ -124,7 +124,7 @@ static struct clk_alpha_pll_postdiv gpll6_out_even = {
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "gpll6_out_even",
 		.parent_hws = (const struct clk_hw*[]){
-			&gpll0.clkr.hw,
+			&gpll6.clkr.hw,
 		},
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
@@ -139,8 +139,8 @@ static struct clk_alpha_pll gpll7 = {
 		.enable_mask = BIT(7),
 		.hw.init = &(struct clk_init_data){
 			.name = "gpll7",
-			.parent_hws = (const struct clk_hw*[]){
-				&gpll0.clkr.hw,
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "bi_tcxo",
 			},
 			.num_parents = 1,
 			.ops = &clk_alpha_pll_fixed_fabia_ops,




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