Patch "clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs" has been added to the 6.9-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs

to the 6.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-clk-alpha-pll-set-alpha_en-bit-for-stromer-.patch
and it can be found in the queue-6.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit e412cb0d807fe5ead4623fa6b4b491840c2dadb5
Author: Gabor Juhos <j4g8y7@xxxxxxxxx>
Date:   Wed May 8 22:34:14 2024 +0200

    clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
    
    [ Upstream commit 5a33a64524e6381c399e5e42571d9363ffc0bed4 ]
    
    The clk_alpha_pll_stromer_plus_set_rate() function does not
    sets the ALPHA_EN bit in the USER_CTL register, so setting
    rates which requires using alpha mode works only if the bit
    gets set already prior calling the function.
    
    Extend the function to set the ALPHA_EN bit in order to allow
    using fractional rates regardless whether the bit gets set
    previously or not.
    
    Fixes: 84da48921a97 ("clk: qcom: clk-alpha-pll: introduce stromer plus ops")
    Signed-off-by: Gabor Juhos <j4g8y7@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20240508-stromer-plus-alpha-en-v1-1-6639ce01ca5b@xxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index be18ff983d35c..003308a288968 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -2555,6 +2555,9 @@ static int clk_alpha_pll_stromer_plus_set_rate(struct clk_hw *hw,
 	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
 					a >> ALPHA_BITWIDTH);
 
+	regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
+			   PLL_ALPHA_EN, PLL_ALPHA_EN);
+
 	regmap_write(pll->clkr.regmap, PLL_MODE(pll), PLL_BYPASSNL);
 
 	/* Wait five micro seconds or more */




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