Patch "RISC-V: fix vector insn load/store width mask" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    RISC-V: fix vector insn load/store width mask

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     risc-v-fix-vector-insn-load-store-width-mask.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 68d660616fe77539ad2b07462f207414c57f1c48
Author: Jesse Taube <jesse@xxxxxxxxxxxx>
Date:   Thu Jun 6 14:28:00 2024 -0400

    RISC-V: fix vector insn load/store width mask
    
    [ Upstream commit 04a2aef59cfe192aa99020601d922359978cc72a ]
    
    RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
    Replace GENMASK(3, 0) with GENMASK(2, 0).
    
    Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
    Signed-off-by: Jesse Taube <jesse@xxxxxxxxxxxx>
    Reviewed-by: Charlie Jenkins <charlie@xxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240606182800.415831-1-jesse@xxxxxxxxxxxx
    Signed-off-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index 06e439eeef9ad..09fde95a5e8f7 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -145,7 +145,7 @@
 
 /* parts of opcode for RVF, RVD and RVQ */
 #define RVFDQ_FL_FS_WIDTH_OFF	12
-#define RVFDQ_FL_FS_WIDTH_MASK	GENMASK(3, 0)
+#define RVFDQ_FL_FS_WIDTH_MASK	GENMASK(2, 0)
 #define RVFDQ_FL_FS_WIDTH_W	2
 #define RVFDQ_FL_FS_WIDTH_D	3
 #define RVFDQ_LS_FS_WIDTH_Q	4




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