Patch "MIPS: Octeon: Add PCIe link status check" has been added to the 6.9-stable tree

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This is a note to let you know that I've just added the patch titled

    MIPS: Octeon: Add PCIe link status check

to the 6.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     mips-octeon-add-pcie-link-status-check.patch
and it can be found in the queue-6.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 7264b262bc2e36cd302e94fff26cc43ebeb3e8c4
Author: Songyang Li <leesongyang@xxxxxxxxxxx>
Date:   Wed Mar 20 23:22:00 2024 +0800

    MIPS: Octeon: Add PCIe link status check
    
    [ Upstream commit 29b83a64df3b42c88c0338696feb6fdcd7f1f3b7 ]
    
    The standard PCIe configuration read-write interface is used to
    access the configuration space of the peripheral PCIe devices
    of the mips processor after the PCIe link surprise down, it can
    generate kernel panic caused by "Data bus error". So it is
    necessary to add PCIe link status check for system protection.
    When the PCIe link is down or in training, assigning a value
    of 0 to the configuration address can prevent read-write behavior
    to the configuration space of peripheral PCIe devices, thereby
    preventing kernel panic.
    
    Signed-off-by: Songyang Li <leesongyang@xxxxxxxxxxx>
    Signed-off-by: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
old mode 100644
new mode 100755
index 2583e318e8c6b..b080c7c6cc463
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -230,12 +230,18 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
 {
 	union cvmx_pcie_address pcie_addr;
 	union cvmx_pciercx_cfg006 pciercx_cfg006;
+	union cvmx_pciercx_cfg032 pciercx_cfg032;
 
 	pciercx_cfg006.u32 =
 	    cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
 	if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
 		return 0;
 
+	pciercx_cfg032.u32 =
+		cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
+	if ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1))
+		return 0;
+
 	pcie_addr.u64 = 0;
 	pcie_addr.config.upper = 2;
 	pcie_addr.config.io = 1;




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