Patch "drm/msm/adreno: fix CP cycles stat retrieval on a7xx" has been added to the 6.9-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/msm/adreno: fix CP cycles stat retrieval on a7xx

to the 6.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-msm-adreno-fix-cp-cycles-stat-retrieval-on-a7xx.patch
and it can be found in the queue-6.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit f515b0742cbe9f36946ab53719dc7cc06bd0a7ea
Author: Zan Dobersek <zdobersek@xxxxxxxxxx>
Date:   Tue Apr 9 14:57:00 2024 +0200

    drm/msm/adreno: fix CP cycles stat retrieval on a7xx
    
    [ Upstream commit 328660262df89ab64031059909d763f7a8af9570 ]
    
    a7xx_submit() should use the a7xx variant of the RBBM_PERFCTR_CP register
    for retrieving the CP cycles value before and after the submitted command
    stream execution.
    
    Signed-off-by: Zan Dobersek <zdobersek@xxxxxxxxxx>
    Fixes: af66706accdf ("drm/msm/a6xx: Add skeleton A7xx support")
    Patchwork: https://patchwork.freedesktop.org/patch/588445/
    Signed-off-by: Rob Clark <robdclark@xxxxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index cf0b1de1c0712..441dfebb36386 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -284,7 +284,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 
 	a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
 
-	get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
+	get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
 		rbmemptr_stats(ring, index, cpcycles_start));
 	get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
 		rbmemptr_stats(ring, index, alwayson_start));
@@ -330,7 +330,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 	OUT_PKT7(ring, CP_SET_MARKER, 1);
 	OUT_RING(ring, 0x00e); /* IB1LIST end */
 
-	get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
+	get_stats_counter(ring, REG_A7XX_RBBM_PERFCTR_CP(0),
 		rbmemptr_stats(ring, index, cpcycles_end));
 	get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER,
 		rbmemptr_stats(ring, index, alwayson_end));




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