Patch "coresight: no-op refactor to make INSTP0 check more idiomatic" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    coresight: no-op refactor to make INSTP0 check more idiomatic

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     coresight-no-op-refactor-to-make-instp0-check-more-i.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit dd76dab03fe3098983f069913b9a148bb3f51ca6
Author: James Clark <james.clark@xxxxxxx>
Date:   Thu Feb 3 11:53:35 2022 +0000

    coresight: no-op refactor to make INSTP0 check more idiomatic
    
    [ Upstream commit d05bbad0130ff86b802e5cd6acbb6cac23b841b8 ]
    
    The spec says this:
    
      P0 tracing support field. The permitted values are:
          0b00  Tracing of load and store instructions as P0 elements is not
                supported.
          0b11  Tracing of load and store instructions as P0 elements is
                supported, so TRCCONFIGR.INSTP0 is supported.
    
                All other values are reserved.
    
    The value we are looking for is 0b11 so simplify this. The double read
    and && was a bit obfuscated.
    
    Suggested-by: Suzuki Poulose <suzuki.poulose@xxxxxxx>
    Signed-off-by: James Clark <james.clark@xxxxxxx>
    Link: https://lore.kernel.org/r/20220203115336.119735-2-james.clark@xxxxxxx
    Signed-off-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
    Stable-dep-of: 46bf8d7cd853 ("coresight: etm4x: Safe access for TRCQCLTR")
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index d3c11e305e5b9..fd753669b33eb 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1048,7 +1048,7 @@ static void etm4_init_arch_data(void *info)
 	etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
 
 	/* INSTP0, bits[2:1] P0 tracing support field */
-	if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
+	if (BMVAL(etmidr0, 1, 2) == 0b11)
 		drvdata->instrp0 = true;
 	else
 		drvdata->instrp0 = false;




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