Patch "clk: mediatek: mt8365-mm: fix DPI0 parent" has been added to the 6.8-stable tree

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This is a note to let you know that I've just added the patch titled

    clk: mediatek: mt8365-mm: fix DPI0 parent

to the 6.8-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-mediatek-mt8365-mm-fix-dpi0-parent.patch
and it can be found in the queue-6.8 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 361c86f27cf94f1ebd53e7c25fd94e4e5f0e8440
Author: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
Date:   Thu Apr 18 16:17:00 2024 +0200

    clk: mediatek: mt8365-mm: fix DPI0 parent
    
    [ Upstream commit 4c0c087772d7e29bc2489ddb068d5167140bfc38 ]
    
    To have a working display through DPI, a workaround has been
    implemented downstream to add "mm_dpi0_dpi0" and "dpi0_sel" to
    the DPI node. Shortly, that add an extra clock.
    
    It seems consistent to have the "dpi0_sel" as parent.
    Additionnaly, "vpll_dpix" isn't used/managed.
    
    Then, set the "mm_dpi0_dpi0" parent clock to "dpi0_sel".
    
    The new clock tree is:
    
    clk26m
      lvdspll
        lvdspll_X (2, 4, 8, 16)
          dpi0_sel
            mm_dpi0_dpi0
    
    Fixes: d46adccb7966 ("clk: mediatek: add driver for MT8365 SoC")
    Signed-off-by: Alexandre Mergnat <amergnat@xxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20231023-display-support-v3-12-53388f3ed34b@xxxxxxxxxxxx
    Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx>
    Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/clk-mt8365-mm.c
index 01a2ef8f594ef..3f62ec7507336 100644
--- a/drivers/clk/mediatek/clk-mt8365-mm.c
+++ b/drivers/clk/mediatek/clk-mt8365-mm.c
@@ -53,7 +53,7 @@ static const struct mtk_gate mm_clks[] = {
 	GATE_MM0(CLK_MM_MM_DSI0, "mm_dsi0", "mm_sel", 17),
 	GATE_MM0(CLK_MM_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 18),
 	GATE_MM0(CLK_MM_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 19),
-	GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
+	GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20),
 	GATE_MM0(CLK_MM_MM_FAKE, "mm_fake", "mm_sel", 21),
 	GATE_MM0(CLK_MM_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 22),
 	GATE_MM0(CLK_MM_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 23),




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