Patch "drm/rockchip: vop2: Do not divide height twice for YUV" has been added to the 6.8-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/rockchip: vop2: Do not divide height twice for YUV

to the 6.8-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-rockchip-vop2-do-not-divide-height-twice-for-yuv.patch
and it can be found in the queue-6.8 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 4b498028ddad3fb6d0aa6611bd48cd96ea87c621
Author: Detlev Casanova <detlev.casanova@xxxxxxxxxxxxx>
Date:   Sun Apr 14 14:27:06 2024 -0400

    drm/rockchip: vop2: Do not divide height twice for YUV
    
    [ Upstream commit e80c219f52861e756181d7f88b0d341116daac2b ]
    
    For the cbcr format, gt2 and gt4 are computed again after src_h has been
    divided by vsub.
    
    As src_h as already been divided by 2 before, introduce cbcr_src_h and
    cbcr_src_w to keep a copy of those values to be used for cbcr gt2 and
    gt4 computation.
    
    This fixes yuv planes being unaligned vertically when down scaling to
    1080 pixels from 2160.
    
    Signed-off-by: Detlev Casanova <detlev.casanova@xxxxxxxxxxxxx>
    Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
    Acked-by: Andy Yan <andy.yan@xxxxxxxxxxxxxx>
    Signed-off-by: Heiko Stuebner <heiko@xxxxxxxxx>
    Link: https://patchwork.freedesktop.org/patch/msgid/20240414182706.655270-1-detlev.casanova@xxxxxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index fdd768bbd487c..62ebbdb16253d 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -706,6 +706,8 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
 	const struct drm_format_info *info;
 	u16 hor_scl_mode, ver_scl_mode;
 	u16 hscl_filter_mode, vscl_filter_mode;
+	uint16_t cbcr_src_w = src_w;
+	uint16_t cbcr_src_h = src_h;
 	u8 gt2 = 0;
 	u8 gt4 = 0;
 	u32 val;
@@ -763,27 +765,27 @@ static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
 	vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
 
 	if (info->is_yuv) {
-		src_w /= info->hsub;
-		src_h /= info->vsub;
+		cbcr_src_w /= info->hsub;
+		cbcr_src_h /= info->vsub;
 
 		gt4 = 0;
 		gt2 = 0;
 
-		if (src_h >= (4 * dst_h)) {
+		if (cbcr_src_h >= (4 * dst_h)) {
 			gt4 = 1;
-			src_h >>= 2;
-		} else if (src_h >= (2 * dst_h)) {
+			cbcr_src_h >>= 2;
+		} else if (cbcr_src_h >= (2 * dst_h)) {
 			gt2 = 1;
-			src_h >>= 1;
+			cbcr_src_h >>= 1;
 		}
 
-		hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
-		ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
+		hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
+		ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 
-		val = vop2_scale_factor(src_w, dst_w);
+		val = vop2_scale_factor(cbcr_src_w, dst_w);
 		vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
 
-		val = vop2_scale_factor(src_h, dst_h);
+		val = vop2_scale_factor(cbcr_src_h, dst_h);
 		vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
 
 		vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);




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