Patch "drm/amd/display: Allocate zero bw after bw alloc enable" has been added to the 6.8-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    drm/amd/display: Allocate zero bw after bw alloc enable

to the 6.8-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amd-display-allocate-zero-bw-after-bw-alloc-enab.patch
and it can be found in the queue-6.8 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 3751b357def7d16d8588fba102eb144d759a0fed
Author: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@xxxxxxx>
Date:   Wed Apr 10 10:46:35 2024 -0400

    drm/amd/display: Allocate zero bw after bw alloc enable
    
    [ Upstream commit 46fe9cb1a9e62f4e6229f48ae303ef8e6c1fdc64 ]
    
    [Why]
    During DP tunnel creation, CM preallocates BW and reduces
    estimated BW of other DPIA. CM release preallocation only
    when allocation is complete. Display mode validation logic
    validates timings based on bw available per host router.
    In multi display setup, this causes bw allocation failure
    when allocation greater than estimated bw.
    
    [How]
    Do zero alloc to make the CM to release preallocation and
    update estimated BW correctly for all DPIAs per host router.
    
    Reviewed-by: PeiChen Huang <peichen.huang@xxxxxxx>
    Acked-by: Aurabindo Pillai <aurabindo.pillai@xxxxxxx>
    Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@xxxxxxx>
    Tested-by: Daniel Wheeler <daniel.wheeler@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index 5491b707cec88..5a965c26bf209 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -270,7 +270,7 @@ static void set_usb4_req_bw_req(struct dc_link *link, int req_bw)
 
 	/* Error check whether requested and allocated are equal */
 	req_bw = requested_bw * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity);
-	if (req_bw == link->dpia_bw_alloc_config.allocated_bw) {
+	if (req_bw && (req_bw == link->dpia_bw_alloc_config.allocated_bw)) {
 		DC_LOG_ERROR("%s: Request bw equals to allocated bw for link(%d)\n",
 			__func__, link->link_index);
 	}
@@ -341,6 +341,14 @@ bool link_dp_dpia_set_dptx_usb4_bw_alloc_support(struct dc_link *link)
 			ret = true;
 			init_usb4_bw_struct(link);
 			link->dpia_bw_alloc_config.bw_alloc_enabled = true;
+
+			/*
+			 * During DP tunnel creation, CM preallocates BW and reduces estimated BW of other
+			 * DPIA. CM release preallocation only when allocation is complete. Do zero alloc
+			 * to make the CM to release preallocation and update estimated BW correctly for
+			 * all DPIAs per host router
+			 */
+			link_dp_dpia_allocate_usb4_bandwidth_for_stream(link, 0);
 		}
 	}