Patch "clk: qcom: dispcc-sm6350: fix DisplayPort clocks" has been added to the 6.9-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    clk: qcom: dispcc-sm6350: fix DisplayPort clocks

to the 6.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-qcom-dispcc-sm6350-fix-displayport-clocks.patch
and it can be found in the queue-6.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 19d53ca725cacbffc4d6638fe8392ba7e32059cc
Author: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Date:   Wed Apr 24 04:39:30 2024 +0300

    clk: qcom: dispcc-sm6350: fix DisplayPort clocks
    
    [ Upstream commit 1113501cfb46d5c0eb960f0a8a9f6c0f91dc6fb6 ]
    
    On SM6350 DisplayPort link clocks use frequency tables inherited from
    the vendor kernel, it is not applicable in the upstream kernel. Drop
    frequency tables and use clk_byte2_ops for those clocks.
    
    This fixes frequency selection in the OPP core (which otherwise attempts
    to use invalid 810 KHz as DP link rate), also fixing the following
    message:
    msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22
    
    Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350")
    Reviewed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
    Tested-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
    Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
    Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240424-dispcc-dp-clocks-v2-2-b44038f3fa96@xxxxxxxxxx
    Signed-off-by: Bjorn Andersson <andersson@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c
index 839435362010e..e4b7464c4d0e9 100644
--- a/drivers/clk/qcom/dispcc-sm6350.c
+++ b/drivers/clk/qcom/dispcc-sm6350.c
@@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
 	},
 };
 
-static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = {
-	F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
-	F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
-	F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
-	F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
-	{ }
-};
-
 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
 	.cmd_rcgr = 0x10f8,
 	.mnd_width = 0,
 	.hid_width = 5,
 	.parent_map = disp_cc_parent_map_0,
-	.freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "disp_cc_mdss_dp_link_clk_src",
 		.parent_data = disp_cc_parent_data_0,
 		.num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 		.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
-		.ops = &clk_rcg2_ops,
+		.ops = &clk_byte2_ops,
 	},
 };