Patch "drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-amdgpu-implement-irq_state_enable-for-sdma-v4.4..patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 9750d903e676890cfebfde3ad68df965dff6b727
Author: Tao Zhou <tao.zhou1@xxxxxxx>
Date:   Thu Mar 28 18:22:10 2024 +0800

    drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2
    
    [ Upstream commit f886b49feaae30acd599e37d4284836024b0f3ed ]
    
    SDMA_CNTL is not set in some cases, driver configures it by itself.
    
    v2: simplify code
    
    Signed-off-by: Tao Zhou <tao.zhou1@xxxxxxx>
    Reviewed-by: Hawking Zhang <Hawking.Zhang@xxxxxxx>
    Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index e76e7e7cb554e..4e8d5e6a65e41 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1613,19 +1613,9 @@ static int sdma_v4_4_2_set_ecc_irq_state(struct amdgpu_device *adev,
 	u32 sdma_cntl;
 
 	sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL);
-	switch (state) {
-	case AMDGPU_IRQ_STATE_DISABLE:
-		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL,
-					  DRAM_ECC_INT_ENABLE, 0);
-		WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
-		break;
-	/* sdma ecc interrupt is enabled by default
-	 * driver doesn't need to do anything to
-	 * enable the interrupt */
-	case AMDGPU_IRQ_STATE_ENABLE:
-	default:
-		break;
-	}
+	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE,
+					state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
+	WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl);
 
 	return 0;
 }




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