Patch "phy: freescale: imx8m-pcie: fix pcie link-up instability" has been added to the 6.1-stable tree

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This is a note to let you know that I've just added the patch titled

    phy: freescale: imx8m-pcie: fix pcie link-up instability

to the 6.1-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     phy-freescale-imx8m-pcie-fix-pcie-link-up-instabilit.patch
and it can be found in the queue-6.1 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 80d015d65c342af28cb0b258577e5be94519677c
Author: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
Date:   Fri Mar 22 14:06:32 2024 +0100

    phy: freescale: imx8m-pcie: fix pcie link-up instability
    
    [ Upstream commit 3a161017f1de55cc48be81f6156004c151f32677 ]
    
    Leaving AUX_PLL_REFCLK_SEL at its reset default of AUX_IN (PLL clock)
    proves to be more stable on the i.MX 8M Mini.
    
    Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver")
    
    Signed-off-by: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
    Reviewed-by: Richard Zhu <hongxing.zhu@xxxxxxx>
    Link: https://lore.kernel.org/r/20240322130646.1016630-2-marcel@xxxxxxxxxxxx
    Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index f1476936b8d9a..211ce84d980f9 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -108,8 +108,10 @@ static int imx8_pcie_phy_power_on(struct phy *phy)
 		/* Source clock from SoC internal PLL */
 		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
-		writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
-		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
+		if (imx8_phy->drvdata->variant != IMX8MM) {
+			writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
+			       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
+		}
 		val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
 		writel(val | ANA_AUX_RX_TERM_GND_EN,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);




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