Patch "phy: rockchip-snps-pcie3: fix bifurcation on rk3588" has been added to the 6.6-stable tree

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



This is a note to let you know that I've just added the patch titled

    phy: rockchip-snps-pcie3: fix bifurcation on rk3588

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     phy-rockchip-snps-pcie3-fix-bifurcation-on-rk3588.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 207ea4cfa5d7da8d04a7560aee5bda50c0fb7c0a
Author: Michal Tomek <mtdev79b@xxxxxxxxx>
Date:   Thu Apr 4 19:11:26 2024 +0200

    phy: rockchip-snps-pcie3: fix bifurcation on rk3588
    
    [ Upstream commit f8020dfb311d2b6cf657668792aaa5fa8863a7dd ]
    
    So far all RK3588 boards use fully aggregated PCIe. CM3588 is one
    of the few boards using this feature and apparently it is broken.
    
    The PHY offers the following mapping options:
    
      port 0 lane 0 - always mapped to controller 0 (4L)
      port 0 lane 1 - to controller 0 or 2 (1L0)
      port 1 lane 0 - to controller 0 or 1 (2L)
      port 1 lane 1 - to controller 0, 1 or 3 (1L1)
    
    The data-lanes DT property maps these as follows:
    
      0 = no controller (unsupported by the HW)
      1 = 4L
      2 = 2L
      3 = 1L0
      4 = 1L1
    
    That allows the following configurations with first column being the
    mainline data-lane mapping, second column being the downstream name,
    third column being PCIE3PHY_GRF_CMN_CON0 and PHP_GRF_PCIESEL register
    values and final column being the user visible lane setup:
    
      <1 1 1 1> = AGGREG = [4 0] = x4 (aggregation)
      <1 1 2 2> = NANBNB = [0 0] = x2 x2 (no bif.)
      <1 3 2 2> = NANBBI = [1 1] = x2 x1x1 (bif. of port 0)
      <1 1 2 4> = NABINB = [2 2] = x1x1 x2 (bif. of port 1)
      <1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports)
    
    The driver currently does not program PHP_GRF_PCIESEL correctly, which
    is fixed by this patch. As a side-effect the new logic is much simpler
    than the old logic.
    
    Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3")
    Signed-off-by: Michal Tomek <mtdev79b@xxxxxxxxx>
    Signed-off-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
    Acked-by: Heiko Stuebner <heiko@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-1-9907136eeafd@xxxxxxxxxx
    Signed-off-by: Vinod Koul <vkoul@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index 121e5961ce114..d5bcc9c42b284 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -132,7 +132,7 @@ static const struct rockchip_p3phy_ops rk3568_ops = {
 static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
 {
 	u32 reg = 0;
-	u8 mode = 0;
+	u8 mode = RK3588_LANE_AGGREGATION; /* default */
 	int ret;
 
 	/* Deassert PCIe PMA output clamp mode */
@@ -140,28 +140,20 @@ static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
 
 	/* Set bifurcation if needed */
 	for (int i = 0; i < priv->num_lanes; i++) {
-		if (!priv->lanes[i])
-			mode |= (BIT(i) << 3);
-
 		if (priv->lanes[i] > 1)
-			mode |= (BIT(i) >> 1);
-	}
-
-	if (!mode)
-		reg = RK3588_LANE_AGGREGATION;
-	else {
-		if (mode & (BIT(0) | BIT(1)))
-			reg |= RK3588_BIFURCATION_LANE_0_1;
-
-		if (mode & (BIT(2) | BIT(3)))
-			reg |= RK3588_BIFURCATION_LANE_2_3;
+			mode &= ~RK3588_LANE_AGGREGATION;
+		if (priv->lanes[i] == 3)
+			mode |= RK3588_BIFURCATION_LANE_0_1;
+		if (priv->lanes[i] == 4)
+			mode |= RK3588_BIFURCATION_LANE_2_3;
 	}
 
+	reg = mode;
 	regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
 
 	/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
 	if (!IS_ERR(priv->pipe_grf)) {
-		reg = (mode & (BIT(6) | BIT(7))) >> 6;
+		reg = mode & 3;
 		if (reg)
 			regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
 				     (reg << 16) | reg);




[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Index of Archives]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite News]     [Linux Kernel]     [Linux SCSI]

  Powered by Linux