Patch "gpio: tegra186: Fix tegra186_gpio_is_accessible() check" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    gpio: tegra186: Fix tegra186_gpio_is_accessible() check

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     gpio-tegra186-fix-tegra186_gpio_is_accessible-check.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 57ee8a18a3272ea19863ae668fbe8d7d0dfb237e
Author: Prathamesh Shete <pshete@xxxxxxxxxx>
Date:   Wed Apr 24 15:25:14 2024 +0530

    gpio: tegra186: Fix tegra186_gpio_is_accessible() check
    
    [ Upstream commit d806f474a9a7993648a2c70642ee129316d8deff ]
    
    The controller has several register bits describing access control
    information for a given GPIO pin. When SCR_SEC_[R|W]EN is unset, it
    means we have full read/write access to all the registers for given GPIO
    pin. When SCR_SEC[R|W]EN is set, it means we need to further check the
    accompanying SCR_SEC_G1[R|W] bit to determine read/write access to all
    the registers for given GPIO pin.
    
    This check was previously declaring that a GPIO pin was accessible
    only if either of the following conditions were met:
    
      - SCR_SEC_REN + SCR_SEC_WEN both set
    
        or
    
      - SCR_SEC_REN + SCR_SEC_WEN both set and
        SCR_SEC_G1R + SCR_SEC_G1W both set
    
    Update the check to properly handle cases where only one of
    SCR_SEC_REN or SCR_SEC_WEN is set.
    
    Fixes: b2b56a163230 ("gpio: tegra186: Check GPIO pin permission before access.")
    Signed-off-by: Prathamesh Shete <pshete@xxxxxxxxxx>
    Acked-by: Thierry Reding <treding@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20240424095514.24397-1-pshete@xxxxxxxxxx
    Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index d87dd06db40d0..9130c691a2dd3 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -36,12 +36,6 @@
 #define  TEGRA186_GPIO_SCR_SEC_REN		BIT(27)
 #define  TEGRA186_GPIO_SCR_SEC_G1W		BIT(9)
 #define  TEGRA186_GPIO_SCR_SEC_G1R		BIT(1)
-#define  TEGRA186_GPIO_FULL_ACCESS		(TEGRA186_GPIO_SCR_SEC_WEN | \
-						 TEGRA186_GPIO_SCR_SEC_REN | \
-						 TEGRA186_GPIO_SCR_SEC_G1R | \
-						 TEGRA186_GPIO_SCR_SEC_G1W)
-#define  TEGRA186_GPIO_SCR_SEC_ENABLE		(TEGRA186_GPIO_SCR_SEC_WEN | \
-						 TEGRA186_GPIO_SCR_SEC_REN)
 
 /* control registers */
 #define TEGRA186_GPIO_ENABLE_CONFIG 0x00
@@ -177,10 +171,18 @@ static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, unsigned
 
 	value = __raw_readl(secure + TEGRA186_GPIO_SCR);
 
-	if ((value & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0)
-		return true;
+	/*
+	 * When SCR_SEC_[R|W]EN is unset, then we have full read/write access to all the
+	 * registers for given GPIO pin.
+	 * When SCR_SEC[R|W]EN is set, then there is need to further check the accompanying
+	 * SCR_SEC_G1[R|W] bit to determine read/write access to all the registers for given
+	 * GPIO pin.
+	 */
 
-	if ((value & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS)
+	if (((value & TEGRA186_GPIO_SCR_SEC_REN) == 0 ||
+	     ((value & TEGRA186_GPIO_SCR_SEC_REN) && (value & TEGRA186_GPIO_SCR_SEC_G1R))) &&
+	     ((value & TEGRA186_GPIO_SCR_SEC_WEN) == 0 ||
+	     ((value & TEGRA186_GPIO_SCR_SEC_WEN) && (value & TEGRA186_GPIO_SCR_SEC_G1W))))
 		return true;
 
 	return false;




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