Patch "drm/i915/cdclk: Fix voltage_level programming edge case" has been added to the 6.6-stable tree

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This is a note to let you know that I've just added the patch titled

    drm/i915/cdclk: Fix voltage_level programming edge case

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-i915-cdclk-fix-voltage_level-programming-edge-ca.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit c964396cda73ba328464682bd4511b1ce408630d
Author: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Date:   Tue Apr 2 18:50:04 2024 +0300

    drm/i915/cdclk: Fix voltage_level programming edge case
    
    [ Upstream commit 6154cc9177ccea00c89ce0bf93352e474b819ff2 ]
    
    Currently we only consider the relationship of the
    old and new CDCLK frequencies when determining whether
    to do the repgramming from intel_set_cdclk_pre_plane_update()
    or intel_set_cdclk_post_plane_update().
    
    It is technically possible to have a situation where the
    CDCLK frequency is decreasing, but the voltage_level is
    increasing due a DDI port. In this case we should bump
    the voltage level already in intel_set_cdclk_pre_plane_update()
    (so that the voltage_level will have been increased by the
    time the port gets enabled), while leaving the CDCLK frequency
    unchanged (as active planes/etc. may still depend on it).
    We can then reduce the CDCLK frequency to its final value
    from intel_set_cdclk_post_plane_update().
    
    In order to handle that correctly we shall construct a
    suitable amalgam of the old and new cdclk states in
    intel_set_cdclk_pre_plane_update().
    
    And we can simply call intel_set_cdclk() unconditionally
    in both places as it will not do anything if nothing actually
    changes vs. the current hw state.
    
    v2: Handle cdclk_state->disable_pipes
    v3: Only synchronize the cd2x update against the pipe's vblank
        when the cdclk frequency is changing during the current
        commit phase (Gustavo)
    
    Cc: stable@xxxxxxxxxxxxxxx
    Cc: Gustavo Sousa <gustavo.sousa@xxxxxxxxx>
    Reviewed-by: Uma Shankar <uma.shankar@xxxxxxxxx>
    Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
    Link: https://patchwork.freedesktop.org/patch/msgid/20240402155016.13733-3-ville.syrjala@xxxxxxxxxxxxxxx
    (cherry picked from commit 34d127e2bdef73a923aa0dcd95cbc3257ad5af52)
    Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 5aa6b998a1cb1..fc3a6eb1de741 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2453,7 +2453,8 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_cdclk_state(state);
 	const struct intel_cdclk_state *new_cdclk_state =
 		intel_atomic_get_new_cdclk_state(state);
-	enum pipe pipe = new_cdclk_state->pipe;
+	struct intel_cdclk_config cdclk_config;
+	enum pipe pipe;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
 				 &new_cdclk_state->actual))
@@ -2462,12 +2463,25 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
 	if (IS_DG2(i915))
 		intel_cdclk_pcode_pre_notify(state);
 
-	if (new_cdclk_state->disable_pipes ||
-	    old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
-		drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+	if (new_cdclk_state->disable_pipes) {
+		cdclk_config = new_cdclk_state->actual;
+		pipe = INVALID_PIPE;
+	} else {
+		if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) {
+			cdclk_config = new_cdclk_state->actual;
+			pipe = new_cdclk_state->pipe;
+		} else {
+			cdclk_config = old_cdclk_state->actual;
+			pipe = INVALID_PIPE;
+		}
 
-		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
+		cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level,
+						 old_cdclk_state->actual.voltage_level);
 	}
+
+	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+
+	intel_set_cdclk(i915, &cdclk_config, pipe);
 }
 
 /**
@@ -2485,7 +2499,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 		intel_atomic_get_old_cdclk_state(state);
 	const struct intel_cdclk_state *new_cdclk_state =
 		intel_atomic_get_new_cdclk_state(state);
-	enum pipe pipe = new_cdclk_state->pipe;
+	enum pipe pipe;
 
 	if (!intel_cdclk_changed(&old_cdclk_state->actual,
 				 &new_cdclk_state->actual))
@@ -2495,11 +2509,14 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
 		intel_cdclk_pcode_post_notify(state);
 
 	if (!new_cdclk_state->disable_pipes &&
-	    old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
-		drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+	    new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk)
+		pipe = new_cdclk_state->pipe;
+	else
+		pipe = INVALID_PIPE;
 
-		intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
-	}
+	drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
+
+	intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
 }
 
 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)




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