This is a note to let you know that I've just added the patch titled
arm64/ptrace: Use saved floating point state type to determine SVE layout
to the 6.6-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
arm64-ptrace-use-saved-floating-point-state-type-to-determine-sve-layout.patch
and it can be found in the queue-6.6 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From b017a0cea627fcbe158fc2c214fe893e18c4d0c4 Mon Sep 17 00:00:00 2001
From: Mark Brown <broonie@xxxxxxxxxx>
Date: Mon, 25 Mar 2024 16:35:21 +0000
Subject: arm64/ptrace: Use saved floating point state type to determine SVE layout
From: Mark Brown <broonie@xxxxxxxxxx>
commit b017a0cea627fcbe158fc2c214fe893e18c4d0c4 upstream.
The SVE register sets have two different formats, one of which is a wrapped
version of the standard FPSIMD register set and another with actual SVE
register data. At present we check TIF_SVE to see if full SVE register
state should be provided when reading the SVE regset but if we were in a
syscall we may have saved only floating point registers even though that is
set.
Fix this and simplify the logic by checking and using the format which we
recorded when deciding if we should use FPSIMD or SVE format.
Fixes: 8c845e273104 ("arm64/sve: Leave SVE enabled on syscall if we don't context switch")
Cc: <stable@xxxxxxxxxxxxxxx> # 6.2.x
Signed-off-by: Mark Brown <broonie@xxxxxxxxxx>
Link: https://lore.kernel.org/r/20240325-arm64-ptrace-fp-type-v1-1-8dc846caf11f@xxxxxxxxxx
Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/arm64/kernel/ptrace.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -728,7 +728,6 @@ static void sve_init_header_from_task(st
{
unsigned int vq;
bool active;
- bool fpsimd_only;
enum vec_type task_type;
memset(header, 0, sizeof(*header));
@@ -744,12 +743,10 @@ static void sve_init_header_from_task(st
case ARM64_VEC_SVE:
if (test_tsk_thread_flag(target, TIF_SVE_VL_INHERIT))
header->flags |= SVE_PT_VL_INHERIT;
- fpsimd_only = !test_tsk_thread_flag(target, TIF_SVE);
break;
case ARM64_VEC_SME:
if (test_tsk_thread_flag(target, TIF_SME_VL_INHERIT))
header->flags |= SVE_PT_VL_INHERIT;
- fpsimd_only = false;
break;
default:
WARN_ON_ONCE(1);
@@ -757,7 +754,7 @@ static void sve_init_header_from_task(st
}
if (active) {
- if (fpsimd_only) {
+ if (target->thread.fp_type == FP_STATE_FPSIMD) {
header->flags |= SVE_PT_REGS_FPSIMD;
} else {
header->flags |= SVE_PT_REGS_SVE;
Patches currently in stable-queue which might be from broonie@xxxxxxxxxx are
queue-6.6/spi-s3c64xx-allow-full-fifo-masks.patch
queue-6.6/arm64-ptrace-use-saved-floating-point-state-type-to-determine-sve-layout.patch
queue-6.6/spi-s3c64xx-remove-else-after-return.patch
queue-6.6/spi-s3c64xx-explicitly-include-linux-bits.h.patch
queue-6.6/asoc-rt722-sdca-sdw-fix-locking-sequence.patch
queue-6.6/asoc-rt711-sdw-fix-locking-sequence.patch
queue-6.6/asoc-ops-fix-wraparound-for-mask-in-snd_soc_get_vols.patch
queue-6.6/spi-s3c64xx-define-a-magic-value.patch
queue-6.6/asoc-wm_adsp-fix-missing-mutex_lock-in-wm_adsp_write.patch
queue-6.6/spi-mchp-pci1xxx-fix-a-possible-null-pointer-derefer.patch
queue-6.6/asoc-rt5682-sdw-fix-locking-sequence.patch
queue-6.6/regmap-maple-fix-uninitialized-symbol-ret-warnings.patch
queue-6.6/asoc-amd-acp-fix-for-acp_init-function-error-handlin.patch
queue-6.6/spi-s3c64xx-determine-the-fifo-depth-only-once.patch
queue-6.6/asoc-sof-amd-fix-for-false-dsp-interrupts.patch
queue-6.6/spi-s3c64xx-use-dma-mode-from-fifo-size.patch
queue-6.6/regmap-maple-fix-cache-corruption-in-regcache_maple_.patch
queue-6.6/spi-s3c64xx-extract-fifo-depth-calculation-to-a-dedi.patch
queue-6.6/asoc-rt711-sdca-fix-locking-sequence.patch
queue-6.6/spi-s3c64xx-sort-headers-alphabetically.patch
queue-6.6/asoc-rt712-sdca-sdw-fix-locking-sequence.patch
