Patch "perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later" has been added to the 6.6-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later

to the 6.6-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     perf-x86-amd-core-update-and-fix-stalled-cycles-even.patch
and it can be found in the queue-6.6 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit ac036d4b549f4d30e977e84a2ae3e3b7b143ec07
Author: Sandipan Das <sandipan.das@xxxxxxx>
Date:   Mon Mar 25 13:17:53 2024 +0530

    perf/x86/amd/core: Update and fix stalled-cycles-* events for Zen 2 and later
    
    [ Upstream commit c7b2edd8377be983442c1344cb940cd2ac21b601 ]
    
    AMD processors based on Zen 2 and later microarchitectures do not
    support PMCx087 (instruction pipe stalls) which is used as the backing
    event for "stalled-cycles-frontend" and "stalled-cycles-backend".
    
    Use PMCx0A9 (cycles where micro-op queue is empty) instead to count
    frontend stalls and remove the entry for backend stalls since there
    is no direct replacement.
    
    Signed-off-by: Sandipan Das <sandipan.das@xxxxxxx>
    Signed-off-by: Ingo Molnar <mingo@xxxxxxxxxx>
    Reviewed-by: Ian Rogers <irogers@xxxxxxxxxx>
    Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h")
    Link: https://lore.kernel.org/r/03d7fc8fa2a28f9be732116009025bdec1b3ec97.1711352180.git.sandipan.das@xxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
index 5365d6acbf090..b30349eeb7678 100644
--- a/arch/x86/events/amd/core.c
+++ b/arch/x86/events/amd/core.c
@@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
 /*
  * AMD Performance Monitor Family 17h and later:
  */
-static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
+static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =
 {
 	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,
 	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
@@ -262,10 +262,24 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
 	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND]	= 0x0187,
 };
 
+static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
+{
+	[PERF_COUNT_HW_CPU_CYCLES]		= 0x0076,
+	[PERF_COUNT_HW_INSTRUCTIONS]		= 0x00c0,
+	[PERF_COUNT_HW_CACHE_REFERENCES]	= 0xff60,
+	[PERF_COUNT_HW_CACHE_MISSES]		= 0x0964,
+	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,
+	[PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,
+	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND]	= 0x00a9,
+};
+
 static u64 amd_pmu_event_map(int hw_event)
 {
-	if (boot_cpu_data.x86 >= 0x17)
-		return amd_f17h_perfmon_event_map[hw_event];
+	if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
+		return amd_zen2_perfmon_event_map[hw_event];
+
+	if (cpu_feature_enabled(X86_FEATURE_ZEN1))
+		return amd_zen1_perfmon_event_map[hw_event];
 
 	return amd_perfmon_event_map[hw_event];
 }