This is a note to let you know that I've just added the patch titled
drm/i915/vrr: Generate VRR "safe window" for DSB
to the 6.8-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-i915-vrr-generate-vrr-safe-window-for-dsb.patch
and it can be found in the queue-6.8 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From f7d3b9277ff7eb8e84e6f8554d1c2dd78278a572 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= <ville.syrjala@xxxxxxxxxxxxxxx>
Date: Wed, 6 Mar 2024 06:08:04 +0200
Subject: drm/i915/vrr: Generate VRR "safe window" for DSB
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From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
commit f7d3b9277ff7eb8e84e6f8554d1c2dd78278a572 upstream.
Looks like TRANS_CHICKEN bit 31 means something totally different
depending on the platform:
TGL: generate VRR "safe window" for DSB
ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
So far we've only set this on ADL/DG2, but when using DSB+VRR
we also need to set it on TGL.
And a quick test on MTL says it doesn't need this bit for either
of those purposes, even though it's still documented as valid
in bspec.
Cc: stable@xxxxxxxxxxxxxxx
Fixes: 34d8311f4a1c ("drm/i915/dsb: Re-instate DSB for LUT updates")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9927
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Link: https://patchwork.freedesktop.org/patch/msgid/20240306040806.21697-2-ville.syrjala@xxxxxxxxxxxxxxx
Reviewed-by: Animesh Manna <animesh.manna@xxxxxxxxx>
(cherry picked from commit 810e4519a1b34b5a0ff0eab32e5b184f533c5ee9)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 7 ++++---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
2 files changed, 5 insertions(+), 4 deletions(-)
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -187,10 +187,11 @@ void intel_vrr_set_transcoder_timings(co
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
/*
- * TRANS_SET_CONTEXT_LATENCY with VRR enabled
- * requires this chicken bit on ADL/DG2.
+ * This bit seems to have two meanings depending on the platform:
+ * TGL: generate VRR "safe window" for DSB vblank waits
+ * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR
*/
- if (DISPLAY_VER(dev_priv) == 13)
+ if (IS_DISPLAY_VER(dev_priv, 12, 13))
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
0, PIPE_VBLANK_WITH_DELAY);
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4597,7 +4597,7 @@
#define MTL_CHICKEN_TRANS(trans) _MMIO_TRANS((trans), \
_MTL_CHICKEN_TRANS_A, \
_MTL_CHICKEN_TRANS_B)
-#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* ADL/DG2 */
+#define PIPE_VBLANK_WITH_DELAY REG_BIT(31) /* tgl+ */
#define SKL_UNMASK_VBL_TO_PIPE_IN_SRD REG_BIT(30) /* skl+ */
#define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
#define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
Patches currently in stable-queue which might be from ville.syrjala@xxxxxxxxxxxxxxx are
queue-6.8/drm-i915-try-to-preserve-the-current-shared_dpll-for-fastset-on-type-c-ports.patch
queue-6.8/drm-i915-pre-populate-the-cursor-physical-dma-address.patch
queue-6.8/drm-i915-replace-a-memset-with-zero-initialization.patch
queue-6.8/drm-i915-add-missing-to-__assign_str-macros-in-trace.patch
queue-6.8/drm-i915-dsi-go-back-to-the-previous-init_otp-display_on-order-mostly.patch
queue-6.8/drm-i915-bios-tolerate-devdata-null-in-intel_bios_encoder_supports_dp_dual_mode.patch
queue-6.8/drm-i915-include-the-pll-name-in-the-debug-messages.patch
queue-6.8/drm-i915-suppress-old-pll-pipe_mask-checks-for-mg-tc-tbt-plls.patch
queue-6.8/drm-i915-dsb-fix-dsb-vblank-waits-when-using-vrr.patch
queue-6.8/drm-i915-vrr-generate-vrr-safe-window-for-dsb.patch
