Patch "iio: adc: rockchip_saradc: use mask for write_enable bitfield" has been added to the 6.7-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    iio: adc: rockchip_saradc: use mask for write_enable bitfield

to the 6.7-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     iio-adc-rockchip_saradc-use-mask-for-write_enable-bi.patch
and it can be found in the queue-6.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit e4843cffbc185091783e25be145b294342dd581a
Author: Quentin Schulz <quentin.schulz@xxxxxxxxxxxxxxxxxxxxx>
Date:   Fri Feb 23 13:45:22 2024 +0100

    iio: adc: rockchip_saradc: use mask for write_enable bitfield
    
    [ Upstream commit 5b4e4b72034f85f7a0cdd147d3d729c5a22c8764 ]
    
    Some of the registers on the SARADCv2 have bits write protected except
    if another bit is set. This is usually done by having the lowest 16 bits
    store the data to write and the highest 16 bits specify which of the 16
    lowest bits should have their value written to the hardware block.
    
    The write_enable mask for the channel selection was incorrect because it
    was just the value shifted by 16 bits, which means it would only ever
    write bits and never clear them. So e.g. if someone starts a conversion
    on channel 5, the lowest 4 bits would be 0x5, then starts a conversion
    on channel 0, it would still be 5.
    
    Instead of shifting the value by 16 as the mask, let's use the OR'ing of
    the appropriate masks shifted by 16.
    
    Note that this is not an issue currently because the only SARADCv2
    currently supported has a reset defined in its Device Tree, that reset
    resets the SARADC controller before starting a conversion on a channel.
    However, this reset is handled as optional by the probe function and
    thus proper masking should be used in the event an SARADCv2 without a
    reset ever makes it upstream.
    
    Fixes: 757953f8ec69 ("iio: adc: rockchip_saradc: Add support for RK3588")
    Signed-off-by: Quentin Schulz <quentin.schulz@xxxxxxxxxxxxxxxxxxxxx>
    Reviewed-by: Heiko Stuebner <heiko@xxxxxxxxx>
    Link: https://lore.kernel.org/r/20240223-saradcv2-chan-mask-v1-2-84b06a0f623a@xxxxxxxxxxxxxxxxxxxxx
    Cc: <Stable@xxxxxxxxxxxxxxx>
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/iio/adc/rockchip_saradc.c b/drivers/iio/adc/rockchip_saradc.c
index 2da8d6f3241a1..1c0042fbbb548 100644
--- a/drivers/iio/adc/rockchip_saradc.c
+++ b/drivers/iio/adc/rockchip_saradc.c
@@ -102,12 +102,12 @@ static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
 	writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
 	writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
 	val = FIELD_PREP(SARADC2_EN_END_INT, 1);
-	val |= val << 16;
+	val |= SARADC2_EN_END_INT << 16;
 	writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
 	val = FIELD_PREP(SARADC2_START, 1) |
 	      FIELD_PREP(SARADC2_SINGLE_MODE, 1) |
 	      FIELD_PREP(SARADC2_CONV_CHANNELS, chn);
-	val |= val << 16;
+	val |= (SARADC2_START | SARADC2_SINGLE_MODE | SARADC2_CONV_CHANNELS) << 16;
 	writel(val, info->regs + SARADC2_CONV_CON);
 }