Patch "net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii" has been added to the 5.15-stable tree

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This is a note to let you know that I've just added the patch titled

    net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii

to the 5.15-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     net-phy-dp83822-enable-rgmii-mode-if-phy_interface_i.patch
and it can be found in the queue-5.15 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit ef1aa16e91cc8fd47206b7b755e5c5330461c404
Author: Tommaso Merciai <tommaso.merciai@xxxxxxxxxxxxxxxxxxxx>
Date:   Sat May 21 01:58:46 2022 +0200

    net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii
    
    [ Upstream commit 621427fbdada788f18f77238e1c36f463c2cb9d1 ]
    
    RGMII mode can be enable from dp83822 straps, and also writing bit 9
    of register 0x17 - RMII and Status Register (RCSR).
    When phy_interface_is_rgmii rgmii mode must be enabled, same for
    contrary, this prevents malconfigurations of hw straps
    
    References:
     - https://www.ti.com/lit/gpn/dp83822i p66
    
    Signed-off-by: Tommaso Merciai <tommaso.merciai@xxxxxxxxxxxxxxxxxxxx>
    Co-developed-by: Michael Trimarchi <michael@xxxxxxxxxxxxxxxxxxxx>
    Suggested-by: Alberto Bianchi <alberto.bianchi@xxxxxxxxxxxxxxxxxxxx>
    Tested-by: Tommaso Merciai <tommaso.merciai@xxxxxxxxxxxxxxxxxxxx>
    Reviewed-by: Andrew Lunn <andrew@xxxxxxx>
    Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
    Stable-dep-of: c8a5c731fd12 ("net: phy: dp83822: Fix RGMII TX delay configuration")
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index f070aa97c77b4..267e6fd3d4448 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -94,7 +94,8 @@
 #define DP83822_WOL_INDICATION_SEL BIT(8)
 #define DP83822_WOL_CLR_INDICATION BIT(11)
 
-/* RSCR bits */
+/* RCSR bits */
+#define DP83822_RGMII_MODE_EN	BIT(9)
 #define DP83822_RX_CLK_SHIFT	BIT(12)
 #define DP83822_TX_CLK_SHIFT	BIT(11)
 
@@ -407,6 +408,12 @@ static int dp83822_config_init(struct phy_device *phydev)
 			if (err)
 				return err;
 		}
+
+		phy_set_bits_mmd(phydev, DP83822_DEVADDR,
+					MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
+	} else {
+		phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
+					MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
 	}
 
 	if (dp83822->fx_enabled) {




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